1 files changed, 97 insertions, 1 deletions

diff --git a/src/cpu/testers/traffic_gen/generators.hh b/src/cpu/testers/traffic_gen/generators.hh
index fe5c5995c..498ef8f37 100644
--- a/src/cpu/testers/traffic_gen/generators.hh
+++ b/src/cpu/testers/traffic_gen/generators.hh
@@ -37,6 +37,7 @@
  * Authors: Thomas Grass
  *          Andreas Hansson
  *          Sascha Bischoff
+ *          Neha Agarwal
  */
 
 /**
@@ -49,6 +50,8 @@
 #ifndef __CPU_TRAFFIC_GEN_GENERATORS_HH__
 #define __CPU_TRAFFIC_GEN_GENERATORS_HH__
 
+#include "base/bitfield.hh"
+#include "base/intmath.hh"
 #include "mem/packet.hh"
 #include "proto/protoio.hh"
 
@@ -273,7 +276,7 @@ class RandomGen : public BaseGen
 
     Tick nextPacketTick(bool elastic, Tick delay) const;
 
-  private:
+  protected:
 
     /** Start of address range */
     const Addr startAddr;
@@ -305,6 +308,99 @@ class RandomGen : public BaseGen
 };
 
 /**
+ * DRAM specific generator is for issuing request with variable page
+ * hit length and bank utilization. Currently assumes a single
+ * channel, single rank configuration.
+ */
+class DramGen : public RandomGen
+{
+
+  public:
+
+    /**
+     * Create a DRAM address sequence generator.
+     *
+     * @param _name Name to use for status and debug
+     * @param master_id MasterID set on each request
+     * @param _duration duration of this state before transitioning
+     * @param start_addr Start address
+     * @param end_addr End address
+     * @param _blocksize Size used for transactions injected
+     * @param min_period Lower limit of random inter-transaction time
+     * @param max_period Upper limit of random inter-transaction time
+     * @param read_percent Percent of transactions that are reads
+     * @param data_limit Upper limit on how much data to read/write
+     * @param num_seq_pkts Number of packets per stride, each of _blocksize
+     * @param page_size Page size (bytes) used in the DRAM
+     * @param nbr_of_banks_DRAM Total number of banks in DRAM
+     * @param nbr_of_banks_util Number of banks to utilized,
+     *                          for N banks, we will use banks: 0->(N-1)
+     * @param addr_mapping Address mapping to be used,
+     *                     0: RoCoRaBaCh, 1: RoRaBaCoCh/RoRaBaChCo
+     *                     assumes single channel and single rank system
+     */
+    DramGen(const std::string& _name, MasterID master_id, Tick _duration,
+            Addr start_addr, Addr end_addr, Addr _blocksize,
+            Tick min_period, Tick max_period,
+            uint8_t read_percent, Addr data_limit,
+            unsigned int num_seq_pkts, unsigned int page_size,
+            unsigned int nbr_of_banks_DRAM, unsigned int nbr_of_banks_util,
+            unsigned int addr_mapping)
+        : RandomGen(_name, master_id, _duration, start_addr, end_addr,
+          _blocksize, min_period, max_period, read_percent, data_limit),
+          numSeqPkts(num_seq_pkts), countNumSeqPkts(0),
+          isRead(true), pageSize(page_size),
+          pageBits(floorLog2(page_size / _blocksize)),
+          bankBits(floorLog2(nbr_of_banks_DRAM)),
+          blockBits(floorLog2(_blocksize)),
+          nbrOfBanksDRAM(nbr_of_banks_DRAM),
+          nbrOfBanksUtil(nbr_of_banks_util), addrMapping(addr_mapping)
+    {
+        if (addrMapping != 1 && addrMapping != 0) {
+            addrMapping = 1;
+            warn("Unknown address mapping specified, using RoRaBaCoCh\n");
+        }
+    }
+
+    PacketPtr getNextPacket();
+
+  private:
+
+    /** Number of sequential DRAM packets to be generated per cpu request */
+    const unsigned int numSeqPkts;
+
+    /** Track number of sequential packets generated for a request  */
+    unsigned int countNumSeqPkts;
+
+    /** Address of request */
+    Addr addr;
+
+    /** Remember type of requests to be generated in series */
+    bool isRead;
+
+    /** Page size of DRAM */
+    const unsigned int pageSize;
+
+    /** Number of page bits in DRAM address */
+    const unsigned int pageBits;
+
+    /** Number of bank bits in DRAM address*/
+    const unsigned int bankBits;
+
+    /** Number of block bits in DRAM address */
+    const unsigned int blockBits;
+
+    /** Number of banks in DRAM */
+    const unsigned int nbrOfBanksDRAM;
+
+    /** Number of banks to be utilized for a given configuration */
+    const unsigned int nbrOfBanksUtil;
+
+    /** Address mapping to be used */
+    unsigned int addrMapping;
+};
+
+/**
  * The trace replay generator reads a trace file and plays
  * back the transactions. The trace is offset with respect to
  * the time when the state was entered.