diff options
Diffstat (limited to 'src/cpu/testers')
| -rw-r--r-- | src/cpu/testers/directedtest/RubyDirectedTester.py | 4 | ||||
| -rw-r--r-- | src/cpu/testers/memtest/MemTest.py | 1 | ||||
| -rw-r--r-- | src/cpu/testers/networktest/NetworkTest.py | 1 | ||||
| -rw-r--r-- | src/cpu/testers/rubytest/RubyTester.py | 1 | ||||
| -rw-r--r-- | src/cpu/testers/traffic_gen/TrafficGen.py | 1 |
5 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py index bf3eace08..f6a625735 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.py +++ b/src/cpu/testers/directedtest/RubyDirectedTester.py @@ -34,20 +34,24 @@ from m5.proxy import * class DirectedGenerator(SimObject): type = 'DirectedGenerator' abstract = True + cxx_header = "cpu/testers/directedtest/DirectedGenerator.hh" num_cpus = Param.Int("num of cpus") system = Param.System(Parent.any, "System we belong to") class SeriesRequestGenerator(DirectedGenerator): type = 'SeriesRequestGenerator' + cxx_header = "cpu/testers/directedtest/SeriesRequestGenerator.hh" addr_increment_size = Param.Int(64, "address increment size") issue_writes = Param.Bool(True, "issue writes if true, otherwise reads") class InvalidateGenerator(DirectedGenerator): type = 'InvalidateGenerator' + cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh" addr_increment_size = Param.Int(64, "address increment size") class RubyDirectedTester(MemObject): type = 'RubyDirectedTester' + cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh" cpuPort = VectorMasterPort("the cpu ports") requests_to_complete = Param.Int("checks to complete") generator = Param.DirectedGenerator("the request generator") diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py index 1b4d6767c..ad3ee9233 100644 --- a/src/cpu/testers/memtest/MemTest.py +++ b/src/cpu/testers/memtest/MemTest.py @@ -32,6 +32,7 @@ from m5.proxy import * class MemTest(MemObject): type = 'MemTest' + cxx_header = "cpu/testers/memtest/memtest.hh" max_loads = Param.Counter(0, "number of loads to execute") atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n") memory_size = Param.Int(65536, "memory size") diff --git a/src/cpu/testers/networktest/NetworkTest.py b/src/cpu/testers/networktest/NetworkTest.py index 7d6ed576b..25b2bb690 100644 --- a/src/cpu/testers/networktest/NetworkTest.py +++ b/src/cpu/testers/networktest/NetworkTest.py @@ -32,6 +32,7 @@ from m5.proxy import * class NetworkTest(MemObject): type = 'NetworkTest' + cxx_header = "cpu/testers/networktest/networktest.hh" block_offset = Param.Int(6, "block offset in bits") num_memories = Param.Int(1, "Num Memories") memory_size = Param.Int(65536, "memory size") diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py index 2eaeb8efd..7af70cae0 100644 --- a/src/cpu/testers/rubytest/RubyTester.py +++ b/src/cpu/testers/rubytest/RubyTester.py @@ -32,6 +32,7 @@ from m5.proxy import * class RubyTester(MemObject): type = 'RubyTester' + cxx_header = "cpu/testers/rubytest/RubyTester.hh" num_cpus = Param.Int("number of cpus / RubyPorts") cpuDataPort = VectorMasterPort("the cpu data cache ports") cpuInstPort = VectorMasterPort("the cpu inst cache ports") diff --git a/src/cpu/testers/traffic_gen/TrafficGen.py b/src/cpu/testers/traffic_gen/TrafficGen.py index 15e9d7a9b..916279f91 100644 --- a/src/cpu/testers/traffic_gen/TrafficGen.py +++ b/src/cpu/testers/traffic_gen/TrafficGen.py @@ -61,6 +61,7 @@ from MemObject import MemObject # probabilities, effectively making it a Markov Chain. class TrafficGen(MemObject): type = 'TrafficGen' + cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh" # Port used for sending requests and receiving responses port = MasterPort("Master port") |