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-rw-r--r--src/cpu/testers/rubytest/CheckTable.cc2
-rw-r--r--src/cpu/testers/rubytest/CheckTable.hh4
-rw-r--r--src/cpu/testers/traffic_gen/traffic_gen.hh11
3 files changed, 9 insertions, 8 deletions
diff --git a/src/cpu/testers/rubytest/CheckTable.cc b/src/cpu/testers/rubytest/CheckTable.cc
index decdd20a2..b75fd0a52 100644
--- a/src/cpu/testers/rubytest/CheckTable.cc
+++ b/src/cpu/testers/rubytest/CheckTable.cc
@@ -112,7 +112,7 @@ CheckTable::getCheck(const Addr address)
{
DPRINTF(RubyTest, "Looking for check by address: %s", address);
- m5::hash_map<Addr, Check*>::iterator i = m_lookup_map.find(address);
+ auto i = m_lookup_map.find(address);
if (i == m_lookup_map.end())
return NULL;
diff --git a/src/cpu/testers/rubytest/CheckTable.hh b/src/cpu/testers/rubytest/CheckTable.hh
index fe7109f26..23ca855d7 100644
--- a/src/cpu/testers/rubytest/CheckTable.hh
+++ b/src/cpu/testers/rubytest/CheckTable.hh
@@ -31,9 +31,9 @@
#define __CPU_RUBYTEST_CHECKTABLE_HH__
#include <iostream>
+#include <unordered_map>
#include <vector>
-#include "base/hashmap.hh"
#include "mem/ruby/common/Address.hh"
class Check;
@@ -63,7 +63,7 @@ class CheckTable
CheckTable& operator=(const CheckTable& obj);
std::vector<Check*> m_check_vector;
- m5::hash_map<Addr, Check*> m_lookup_map;
+ std::unordered_map<Addr, Check*> m_lookup_map;
int m_num_writers;
int m_num_readers;
diff --git a/src/cpu/testers/traffic_gen/traffic_gen.hh b/src/cpu/testers/traffic_gen/traffic_gen.hh
index 8b71443f9..e5295bcf5 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.hh
+++ b/src/cpu/testers/traffic_gen/traffic_gen.hh
@@ -41,7 +41,8 @@
#ifndef __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
#define __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
-#include "base/hashmap.hh"
+#include <unordered_map>
+
#include "base/statistics.hh"
#include "cpu/testers/traffic_gen/generators.hh"
#include "mem/mem_object.hh"
@@ -135,7 +136,7 @@ class TrafficGen : public MemObject
uint32_t currState;
/** Map of generator states */
- m5::hash_map<uint32_t, BaseGen*> states;
+ std::unordered_map<uint32_t, BaseGen*> states;
/** Master port specialisation for the traffic generator */
class TrafficGenPort : public MasterPort
@@ -198,10 +199,10 @@ class TrafficGen : public MemObject
void initState();
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/** Register statistics */
void regStats();