diff options
Diffstat (limited to 'src/cpu/thread_context.cc')
| -rw-r--r-- | src/cpu/thread_context.cc | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc index cea21e790..0d288de6f 100644 --- a/src/cpu/thread_context.cc +++ b/src/cpu/thread_context.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012 ARM Limited + * Copyright (c) 2012, 2016 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -76,6 +76,16 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two) panic("Float reg idx %d doesn't match, one: %#x, two: %#x", i, t1, t2); } + + // Then loop through the vector registers. + for (int i = 0; i < TheISA::NumVecRegs; ++i) { + RegId rid(VecRegClass, i); + const TheISA::VecRegContainer& t1 = one->readVecReg(rid); + const TheISA::VecRegContainer& t2 = two->readVecReg(rid); + if (t1 != t2) + panic("Vec reg idx %d doesn't match, one: %#x, two: %#x", + i, t1, t2); + } for (int i = 0; i < TheISA::NumMiscRegs; ++i) { TheISA::MiscReg t1 = one->readMiscRegNoEffect(i); TheISA::MiscReg t2 = two->readMiscRegNoEffect(i); @@ -152,6 +162,12 @@ serialize(ThreadContext &tc, CheckpointOut &cp) // compatibility. arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs); + std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs); + for (int i = 0; i < NumVecRegs; ++i) { + vecRegs[i] = tc.readVecRegFlat(i); + } + SERIALIZE_CONTAINER(vecRegs); + IntReg intRegs[NumIntRegs]; for (int i = 0; i < NumIntRegs; ++i) intRegs[i] = tc.readIntRegFlat(i); @@ -181,6 +197,12 @@ unserialize(ThreadContext &tc, CheckpointIn &cp) for (int i = 0; i < NumFloatRegs; ++i) tc.setFloatRegBitsFlat(i, floatRegs[i]); + std::vector<TheISA::VecRegContainer> vecRegs(NumVecRegs); + UNSERIALIZE_CONTAINER(vecRegs); + for (int i = 0; i < NumVecRegs; ++i) { + tc.setVecRegFlat(i, vecRegs[i]); + } + IntReg intRegs[NumIntRegs]; UNSERIALIZE_ARRAY(intRegs, NumIntRegs); for (int i = 0; i < NumIntRegs; ++i) |