diff options
Diffstat (limited to 'src/cpu/thread_context.cc')
| -rw-r--r-- | src/cpu/thread_context.cc | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc index fe1ae69dd..ce7604d3c 100644 --- a/src/cpu/thread_context.cc +++ b/src/cpu/thread_context.cc @@ -88,6 +88,15 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two) panic("CC reg idx %d doesn't match, one: %#x, two: %#x", i, t1, t2); } + + // loop through the Vector registers. + for (int i = 0; i < TheISA::NumVectorRegs; ++i) { + const TheISA::VectorReg &t1 = one->readVectorReg(i); + const TheISA::VectorReg &t2 = two->readVectorReg(i); + if (t1 != t2) + panic("Vector reg idx %d doesn't match", i); + } + if (!(one->pcState() == two->pcState())) panic("PC state doesn't match."); int id1 = one->cpuId(); @@ -127,6 +136,16 @@ serialize(ThreadContext &tc, CheckpointOut &cp) SERIALIZE_ARRAY(ccRegs, NumCCRegs); #endif +#ifdef ISA_HAS_VECTOR_REGS + VectorRegElement vectorRegs[NumVectorRegs * NumVectorRegElements]; + for (int i = 0; i < NumVectorRegs; ++i) { + const VectorReg &v = tc.readVectorRegFlat(i); + for (int j = 0; i < NumVectorRegElements; ++j) + vectorRegs[i * NumVectorRegElements + j] = v[j]; + } + SERIALIZE_ARRAY(vectorRegs, NumVectorRegs * NumVectorRegElements); +#endif + tc.pcState().serialize(cp); // thread_num and cpu_id are deterministic from the config @@ -156,6 +175,17 @@ unserialize(ThreadContext &tc, CheckpointIn &cp) tc.setCCRegFlat(i, ccRegs[i]); #endif +#ifdef ISA_HAS_VECTOR_REGS + VectorRegElement vectorRegs[NumVectorRegs * NumVectorRegElements]; + UNSERIALIZE_ARRAY(vectorRegs, NumVectorRegs * NumVectorRegElements); + for (int i = 0; i < NumVectorRegs; ++i) { + VectorReg v; + for (int j = 0; i < NumVectorRegElements; ++j) + v[j] = vectorRegs[i * NumVectorRegElements + j]; + tc.setVectorRegFlat(i, v); + } +#endif + PCState pcState; pcState.unserialize(cp); tc.pcState(pcState); |