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-rw-r--r--src/cpu/thread_context.hh5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 0f7228f0c..3b7f8b3c3 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -48,6 +48,7 @@ namespace TheISA
}
class BaseCPU;
class Checkpoint;
+class Decoder;
class EndQuiesceEvent;
class TranslatingPort;
class FunctionalPort;
@@ -120,6 +121,8 @@ class ThreadContext
virtual TheISA::TLB *getDTBPtr() = 0;
+ virtual Decoder *getDecoderPtr() = 0;
+
virtual System *getSystemPtr() = 0;
#if FULL_SYSTEM
@@ -287,6 +290,8 @@ class ProxyThreadContext : public ThreadContext
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
+ Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
+
System *getSystemPtr() { return actualTC->getSystemPtr(); }
#if FULL_SYSTEM