1 files changed, 1 insertions, 12 deletions
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 72c9df33d..ca649b40e 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -87,14 +87,9 @@ class ThreadContext
     typedef TheISA::MiscRegFile MiscRegFile;
     typedef TheISA::MiscReg MiscReg;
   public:
+
     enum Status
     {
-        /// Initialized but not running yet.  All CPUs start in
-        /// this state, but most transition to Active on cycle 1.
-        /// In MP or SMT systems, non-primary contexts will stay
-        /// in this state until a thread is assigned to them.
-        Unallocated,
-
         /// Running.  Instructions should be executed only when
         /// the context is in this state.
         Active,
@@ -154,9 +149,6 @@ class ThreadContext
     /// Set the status to Suspended.
     virtual void suspend(int delay = 0) = 0;
 
-    /// Set the status to Unallocated.
-    virtual void deallocate(int delay = 0) = 0;
-
     /// Set the status to Halted.
     virtual void halt(int delay = 0) = 0;
 
@@ -337,9 +329,6 @@ class ProxyThreadContext : public ThreadContext
     /// Set the status to Suspended.
     void suspend(int delay = 0) { actualTC->suspend(); }
 
-    /// Set the status to Unallocated.
-    void deallocate(int delay = 0) { actualTC->deallocate(); }
-
     /// Set the status to Halted.
     void halt(int delay = 0) { actualTC->halt(); }