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-rw-r--r--src/cpu/base.hh6
-rw-r--r--src/cpu/checker/cpu.hh6
-rw-r--r--src/cpu/decode_cache.hh9
-rw-r--r--src/cpu/inst_pb_trace.hh4
-rw-r--r--src/cpu/kvm/base.hh12
-rw-r--r--src/cpu/kvm/x86_cpu.hh2
-rw-r--r--src/cpu/minor/cpu.hh11
-rw-r--r--src/cpu/minor/pipeline.hh2
-rw-r--r--src/cpu/o3/cpu.hh11
-rw-r--r--src/cpu/o3/lsq_unit.hh1
-rw-r--r--src/cpu/o3/mem_dep_unit.hh4
-rw-r--r--src/cpu/o3/thread_state.hh4
-rw-r--r--src/cpu/pred/bpred_unit.hh2
-rw-r--r--src/cpu/simple/atomic.hh4
-rw-r--r--src/cpu/simple/base.hh7
-rw-r--r--src/cpu/simple/exec_context.hh74
-rw-r--r--src/cpu/simple/probes/simpoint.hh9
-rw-r--r--src/cpu/simple/timing.hh4
-rw-r--r--src/cpu/simple_thread.hh4
-rw-r--r--src/cpu/testers/rubytest/CheckTable.cc2
-rw-r--r--src/cpu/testers/rubytest/CheckTable.hh4
-rw-r--r--src/cpu/testers/traffic_gen/traffic_gen.hh11
-rw-r--r--src/cpu/thread_state.hh4
23 files changed, 95 insertions, 102 deletions
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 95ae4fc43..554c4d754 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -307,7 +307,7 @@ class BaseCPU : public MemObject
virtual void startup();
virtual void regStats();
- void regProbePoints() M5_ATTR_OVERRIDE;
+ void regProbePoints() override;
void registerThreadContexts();
@@ -399,7 +399,7 @@ class BaseCPU : public MemObject
*
* @param os The stream to serialize to.
*/
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
/**
* Reconstruct the state of this object from a checkpoint.
@@ -412,7 +412,7 @@ class BaseCPU : public MemObject
* @param cp The checkpoint use.
* @param section The section name of this object.
*/
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void unserialize(CheckpointIn &cp) override;
/**
* Serialize a single thread.
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 0351ec2e0..14c0ad0b2 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -189,8 +189,8 @@ class CheckerCPU : public BaseCPU, public ExecContext
Counter numLoad;
Counter startNumLoad;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
// These functions are only used in CPU models that split
// effective address computation from the actual memory access.
@@ -380,7 +380,7 @@ class CheckerCPU : public BaseCPU, public ExecContext
Fault hwrei() { return thread->hwrei(); }
bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
- void wakeup(ThreadID tid) M5_ATTR_OVERRIDE { }
+ void wakeup(ThreadID tid) override { }
// Assume that the normal CPU's call to syscall was successful.
// The checker's state would have already been updated by the syscall.
void syscall(int64_t callnum) { }
diff --git a/src/cpu/decode_cache.hh b/src/cpu/decode_cache.hh
index 34387419f..c451cbb69 100644
--- a/src/cpu/decode_cache.hh
+++ b/src/cpu/decode_cache.hh
@@ -31,9 +31,10 @@
#ifndef __CPU_DECODE_CACHE_HH__
#define __CPU_DECODE_CACHE_HH__
+#include <unordered_map>
+
#include "arch/isa_traits.hh"
#include "arch/types.hh"
-#include "base/hashmap.hh"
#include "config/the_isa.hh"
#include "cpu/static_inst_fwd.hh"
@@ -46,7 +47,7 @@ namespace DecodeCache
{
/// Hash for decoded instructions.
-typedef m5::hash_map<TheISA::ExtMachInst, StaticInstPtr> InstMap;
+typedef std::unordered_map<TheISA::ExtMachInst, StaticInstPtr> InstMap;
/// A sparse map from an Addr to a Value, stored in page chunks.
template<class Value>
@@ -58,7 +59,7 @@ class AddrMap
Value items[TheISA::PageBytes];
};
// A map of cache pages which allows a sparse mapping.
- typedef typename m5::hash_map<Addr, CachePage *> PageMap;
+ typedef typename std::unordered_map<Addr, CachePage *> PageMap;
typedef typename PageMap::iterator PageIt;
// Mini cache of recent lookups.
PageIt recent[2];
@@ -75,7 +76,7 @@ class AddrMap
/// Attempt to find the CacheePage which goes with a particular
/// address. First check the small cache of recent results, then
- /// actually look in the hash_map.
+ /// actually look in the hash map.
/// @param addr The address to look up.
CachePage *
getPage(Addr addr)
diff --git a/src/cpu/inst_pb_trace.hh b/src/cpu/inst_pb_trace.hh
index bdafb6245..57b3c2c59 100644
--- a/src/cpu/inst_pb_trace.hh
+++ b/src/cpu/inst_pb_trace.hh
@@ -75,7 +75,7 @@ class InstPBTraceRecord : public InstRecord
* This implementation of dump calls InstPBTrace to output the contents to a
* protobuf file
*/
- void dump() M5_ATTR_OVERRIDE;
+ void dump() override;
protected:
InstPBTrace& tracer;
@@ -90,7 +90,7 @@ class InstPBTrace : public InstTracer
InstPBTraceRecord* getInstRecord(Tick when, ThreadContext *tc, const
StaticInstPtr si, TheISA::PCState pc, const
- StaticInstPtr mi = NULL) M5_ATTR_OVERRIDE;
+ StaticInstPtr mi = NULL) override;
protected:
/** One output stream for the entire simulation.
diff --git a/src/cpu/kvm/base.hh b/src/cpu/kvm/base.hh
index 89c52cf6b..d57ac3421 100644
--- a/src/cpu/kvm/base.hh
+++ b/src/cpu/kvm/base.hh
@@ -84,13 +84,11 @@ class BaseKvmCPU : public BaseCPU
void startup();
void regStats();
- void serializeThread(CheckpointOut &cp,
- ThreadID tid) const M5_ATTR_OVERRIDE;
- void unserializeThread(CheckpointIn &cp,
- ThreadID tid) M5_ATTR_OVERRIDE;
+ void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
+ void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
- DrainState drain() M5_ATTR_OVERRIDE;
- void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ void drainResume() override;
void switchOut();
void takeOverFrom(BaseCPU *cpu);
@@ -100,7 +98,7 @@ class BaseKvmCPU : public BaseCPU
MasterPort &getDataPort() { return dataPort; }
MasterPort &getInstPort() { return instPort; }
- void wakeup(ThreadID tid = 0) M5_ATTR_OVERRIDE;
+ void wakeup(ThreadID tid = 0) override;
void activateContext(ThreadID thread_num);
void suspendContext(ThreadID thread_num);
void deallocateContext(ThreadID thread_num);
diff --git a/src/cpu/kvm/x86_cpu.hh b/src/cpu/kvm/x86_cpu.hh
index 2e93a5f26..14f16d544 100644
--- a/src/cpu/kvm/x86_cpu.hh
+++ b/src/cpu/kvm/x86_cpu.hh
@@ -47,7 +47,7 @@ class X86KvmCPU : public BaseKvmCPU
void startup();
/** @{ */
- void dump() const M5_ATTR_OVERRIDE;
+ void dump() const override;
void dumpFpuRegs() const;
void dumpIntRegs() const;
void dumpSpecRegs() const;
diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh
index 99b915693..5bfc3b29f 100644
--- a/src/cpu/minor/cpu.hh
+++ b/src/cpu/minor/cpu.hh
@@ -128,7 +128,7 @@ class MinorCPU : public BaseCPU
/** Starting, waking and initialisation */
void init();
void startup();
- void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
+ void wakeup(ThreadID tid) override;
Addr dbg_vtophys(Addr addr);
@@ -142,17 +142,16 @@ class MinorCPU : public BaseCPU
Counter totalInsts() const;
Counter totalOps() const;
- void serializeThread(CheckpointOut &cp,
- ThreadID tid) const M5_ATTR_OVERRIDE;
- void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
+ void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
+ void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
/** Serialize pipeline data */
void serialize(CheckpointOut &cp) const;
void unserialize(CheckpointIn &cp);
/** Drain interface */
- DrainState drain() M5_ATTR_OVERRIDE;
- void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ void drainResume() override;
/** Signal from Pipeline that MinorCPU should signal that a drain
* is complete and set its drainState */
void signalDrainDone();
diff --git a/src/cpu/minor/pipeline.hh b/src/cpu/minor/pipeline.hh
index bf2071b02..213def58e 100644
--- a/src/cpu/minor/pipeline.hh
+++ b/src/cpu/minor/pipeline.hh
@@ -126,7 +126,7 @@ class Pipeline : public Ticked
* stages and pipeline advance) */
void evaluate();
- void countCycles(Cycles delta) M5_ATTR_OVERRIDE
+ void countCycles(Cycles delta) override
{
cpu.ppCycles->notify(delta);
}
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index bd9c44752..bed61234a 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -338,9 +338,8 @@ class FullO3CPU : public BaseO3CPU
/** Is the CPU draining? */
bool isDraining() const { return drainState() == DrainState::Draining; }
- void serializeThread(CheckpointOut &cp,
- ThreadID tid) const M5_ATTR_OVERRIDE;
- void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
+ void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
+ void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
public:
/** Executes a syscall.
@@ -350,10 +349,10 @@ class FullO3CPU : public BaseO3CPU
/** Starts draining the CPU's pipeline of all instructions in
* order to stop all memory accesses. */
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
/** Resumes execution after a drain. */
- void drainResume() M5_ATTR_OVERRIDE;
+ void drainResume() override;
/**
* Commit has reached a safe point to drain a thread.
@@ -640,7 +639,7 @@ class FullO3CPU : public BaseO3CPU
/** Wakes the CPU, rescheduling the CPU if it's not already active. */
void wakeCPU();
- virtual void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
+ virtual void wakeup(ThreadID tid) override;
/** Gets a free thread id. Use if thread ids change across system. */
ThreadID getFreeTid();
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index e356dd442..039bba8b6 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -54,7 +54,6 @@
#include "arch/isa_traits.hh"
#include "arch/locked_mem.hh"
#include "arch/mmapped_ipr.hh"
-#include "base/hashmap.hh"
#include "config/the_isa.hh"
#include "cpu/inst_seq.hh"
#include "cpu/timebuf.hh"
diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh
index c2c411fe4..ffe66be6b 100644
--- a/src/cpu/o3/mem_dep_unit.hh
+++ b/src/cpu/o3/mem_dep_unit.hh
@@ -46,8 +46,8 @@
#include <list>
#include <memory>
#include <set>
+#include <unordered_map>
-#include "base/hashmap.hh"
#include "base/statistics.hh"
#include "cpu/inst_seq.hh"
#include "debug/MemDepUnit.hh"
@@ -237,7 +237,7 @@ class MemDepUnit
/** Moves an entry to the ready list. */
inline void moveToReady(MemDepEntryPtr &ready_inst_entry);
- typedef m5::hash_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
+ typedef std::unordered_map<InstSeqNum, MemDepEntryPtr, SNHash> MemDepHash;
typedef typename MemDepHash::iterator MemDepHashIt;
diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh
index cf9403e48..19235c44c 100644
--- a/src/cpu/o3/thread_state.hh
+++ b/src/cpu/o3/thread_state.hh
@@ -112,7 +112,7 @@ struct O3ThreadState : public ThreadState {
profilePC = 3;
}
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE
+ void serialize(CheckpointOut &cp) const override
{
ThreadState::serialize(cp);
// Use the ThreadContext serialization helper to serialize the
@@ -120,7 +120,7 @@ struct O3ThreadState : public ThreadState {
::serialize(*tc, cp);
}
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE
+ void unserialize(CheckpointIn &cp) override
{
// Prevent squashing - we don't have any instructions in
// flight that we need to squash since we just instantiated a
diff --git a/src/cpu/pred/bpred_unit.hh b/src/cpu/pred/bpred_unit.hh
index f8b217567..1f26f1aac 100644
--- a/src/cpu/pred/bpred_unit.hh
+++ b/src/cpu/pred/bpred_unit.hh
@@ -77,7 +77,7 @@ class BPredUnit : public SimObject
*/
void regStats();
- void regProbePoints() M5_ATTR_OVERRIDE;
+ void regProbePoints() override;
/** Perform sanity checks after a drain. */
void drainSanityCheck() const;
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 2bea12ab2..372df7cbd 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -191,8 +191,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
public:
- DrainState drain() M5_ATTR_OVERRIDE;
- void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ void drainResume() override;
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 1fcd5c203..72ac9bb4b 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -93,7 +93,7 @@ class BaseSimpleCPU : public BaseCPU
public:
BaseSimpleCPU(BaseSimpleCPUParams *params);
virtual ~BaseSimpleCPU();
- void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
+ void wakeup(ThreadID tid) override;
virtual void init();
public:
Trace::InstRecord *traceData;
@@ -152,9 +152,8 @@ class BaseSimpleCPU : public BaseCPU
virtual Counter totalInsts() const;
virtual Counter totalOps() const;
- void serializeThread(CheckpointOut &cp,
- ThreadID tid) const M5_ATTR_OVERRIDE;
- void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
+ void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
+ void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
};
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 591cf8227..43a012404 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -160,23 +160,21 @@ class SimpleExecContext : public ExecContext {
{ }
/** Reads an integer register. */
- IntReg readIntRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
+ IntReg readIntRegOperand(const StaticInst *si, int idx) override
{
numIntRegReads++;
return thread->readIntReg(si->srcRegIdx(idx));
}
/** Sets an integer register to a value. */
- void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
- M5_ATTR_OVERRIDE
+ void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
{
numIntRegWrites++;
thread->setIntReg(si->destRegIdx(idx), val);
}
/** Reads a floating point register of single register width. */
- FloatReg readFloatRegOperand(const StaticInst *si, int idx)
- M5_ATTR_OVERRIDE
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
{
numFpRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
@@ -185,8 +183,7 @@ class SimpleExecContext : public ExecContext {
/** Reads a floating point register in its binary format, instead
* of by value. */
- FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
- M5_ATTR_OVERRIDE
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override
{
numFpRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
@@ -194,8 +191,8 @@ class SimpleExecContext : public ExecContext {
}
/** Sets a floating point register of single width to a value. */
- void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
- M5_ATTR_OVERRIDE
+ void setFloatRegOperand(const StaticInst *si, int idx,
+ FloatReg val) override
{
numFpRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
@@ -205,37 +202,36 @@ class SimpleExecContext : public ExecContext {
/** Sets the bits of a floating point register of single width
* to a binary value. */
void setFloatRegOperandBits(const StaticInst *si, int idx,
- FloatRegBits val) M5_ATTR_OVERRIDE
+ FloatRegBits val) override
{
numFpRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
thread->setFloatRegBits(reg_idx, val);
}
- CCReg readCCRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
+ CCReg readCCRegOperand(const StaticInst *si, int idx) override
{
numCCRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
return thread->readCCReg(reg_idx);
}
- void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
- M5_ATTR_OVERRIDE
+ void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
{
numCCRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
thread->setCCReg(reg_idx, val);
}
- MiscReg readMiscRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
+ MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
{
numIntRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
return thread->readMiscReg(reg_idx);
}
- void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
- M5_ATTR_OVERRIDE
+ void setMiscRegOperand(const StaticInst *si, int idx,
+ const MiscReg &val) override
{
numIntRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
@@ -246,7 +242,7 @@ class SimpleExecContext : public ExecContext {
* Reads a miscellaneous register, handling any architectural
* side effects due to reading that register.
*/
- MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE
+ MiscReg readMiscReg(int misc_reg) override
{
numIntRegReads++;
return thread->readMiscReg(misc_reg);
@@ -256,18 +252,18 @@ class SimpleExecContext : public ExecContext {
* Sets a miscellaneous register, handling any architectural
* side effects due to writing that register.
*/
- void setMiscReg(int misc_reg, const MiscReg &val) M5_ATTR_OVERRIDE
+ void setMiscReg(int misc_reg, const MiscReg &val) override
{
numIntRegWrites++;
thread->setMiscReg(misc_reg, val);
}
- PCState pcState() const M5_ATTR_OVERRIDE
+ PCState pcState() const override
{
return thread->pcState();
}
- void pcState(const PCState &val) M5_ATTR_OVERRIDE
+ void pcState(const PCState &val) override
{
thread->pcState(val);
}
@@ -278,7 +274,7 @@ class SimpleExecContext : public ExecContext {
*
* @note Only valid for memory ops.
*/
- void setEA(Addr EA) M5_ATTR_OVERRIDE
+ void setEA(Addr EA) override
{ panic("BaseSimpleCPU::setEA() not implemented\n"); }
/**
@@ -286,17 +282,17 @@ class SimpleExecContext : public ExecContext {
*
* @note Only valid for memory ops.
*/
- Addr getEA() const M5_ATTR_OVERRIDE
+ Addr getEA() const override
{ panic("BaseSimpleCPU::getEA() not implemented\n"); }
Fault readMem(Addr addr, uint8_t *data, unsigned int size,
- unsigned int flags) M5_ATTR_OVERRIDE
+ unsigned int flags) override
{
return cpu->readMem(addr, data, size, flags);
}
Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
- unsigned int flags, uint64_t *res) M5_ATTR_OVERRIDE
+ unsigned int flags, uint64_t *res) override
{
return cpu->writeMem(data, size, addr, flags, res);
}
@@ -304,7 +300,7 @@ class SimpleExecContext : public ExecContext {
/**
* Sets the number of consecutive store conditional failures.
*/
- void setStCondFailures(unsigned int sc_failures) M5_ATTR_OVERRIDE
+ void setStCondFailures(unsigned int sc_failures) override
{
thread->setStCondFailures(sc_failures);
}
@@ -312,7 +308,7 @@ class SimpleExecContext : public ExecContext {
/**
* Returns the number of consecutive store conditional failures.
*/
- unsigned int readStCondFailures() const M5_ATTR_OVERRIDE
+ unsigned int readStCondFailures() const override
{
return thread->readStCondFailures();
}
@@ -320,7 +316,7 @@ class SimpleExecContext : public ExecContext {
/**
* Executes a syscall specified by the callnum.
*/
- void syscall(int64_t callnum) M5_ATTR_OVERRIDE
+ void syscall(int64_t callnum) override
{
if (FullSystem)
panic("Syscall emulation isn't available in FS mode.");
@@ -329,7 +325,7 @@ class SimpleExecContext : public ExecContext {
}
/** Returns a pointer to the ThreadContext. */
- ThreadContext *tcBase() M5_ATTR_OVERRIDE
+ ThreadContext *tcBase() override
{
return thread->getTC();
}
@@ -338,7 +334,7 @@ class SimpleExecContext : public ExecContext {
* Somewhat Alpha-specific function that handles returning from an
* error or interrupt.
*/
- Fault hwrei() M5_ATTR_OVERRIDE
+ Fault hwrei() override
{
return thread->hwrei();
}
@@ -347,17 +343,17 @@ class SimpleExecContext : public ExecContext {
* Check for special simulator handling of specific PAL calls. If
* return value is false, actual PAL call will be suppressed.
*/
- bool simPalCheck(int palFunc) M5_ATTR_OVERRIDE
+ bool simPalCheck(int palFunc) override
{
return thread->simPalCheck(palFunc);
}
- bool readPredicate() M5_ATTR_OVERRIDE
+ bool readPredicate() override
{
return thread->readPredicate();
}
- void setPredicate(bool val) M5_ATTR_OVERRIDE
+ void setPredicate(bool val) override
{
thread->setPredicate(val);
@@ -369,41 +365,41 @@ class SimpleExecContext : public ExecContext {
/**
* Invalidate a page in the DTLB <i>and</i> ITLB.
*/
- void demapPage(Addr vaddr, uint64_t asn) M5_ATTR_OVERRIDE
+ void demapPage(Addr vaddr, uint64_t asn) override
{
thread->demapPage(vaddr, asn);
}
- void armMonitor(Addr address) M5_ATTR_OVERRIDE
+ void armMonitor(Addr address) override
{
cpu->armMonitor(thread->threadId(), address);
}
- bool mwait(PacketPtr pkt) M5_ATTR_OVERRIDE
+ bool mwait(PacketPtr pkt) override
{
return cpu->mwait(thread->threadId(), pkt);
}
- void mwaitAtomic(ThreadContext *tc) M5_ATTR_OVERRIDE
+ void mwaitAtomic(ThreadContext *tc) override
{
cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb);
}
- AddressMonitor *getAddrMonitor() M5_ATTR_OVERRIDE
+ AddressMonitor *getAddrMonitor() override
{
return cpu->getCpuAddrMonitor(thread->threadId());
}
#if THE_ISA == MIPS_ISA
MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
- M5_ATTR_OVERRIDE
+ override
{
panic("Simple CPU models do not support multithreaded "
"register access.");
}
void setRegOtherThread(int regIdx, MiscReg val,
- ThreadID tid = InvalidThreadID) M5_ATTR_OVERRIDE
+ ThreadID tid = InvalidThreadID) override
{
panic("Simple CPU models do not support multithreaded "
"register access.");
diff --git a/src/cpu/simple/probes/simpoint.hh b/src/cpu/simple/probes/simpoint.hh
index e2c343755..2f4ed080d 100644
--- a/src/cpu/simple/probes/simpoint.hh
+++ b/src/cpu/simple/probes/simpoint.hh
@@ -41,7 +41,8 @@
#ifndef __CPU_SIMPLE_PROBES_SIMPOINT_HH__
#define __CPU_SIMPLE_PROBES_SIMPOINT_HH__
-#include "base/hashmap.hh"
+#include <unordered_map>
+
#include "cpu/simple_thread.hh"
#include "params/SimPoint.hh"
#include "sim/probe/probe.hh"
@@ -59,7 +60,7 @@
typedef std::pair<Addr, Addr> BasicBlockRange;
/** Overload hash function for BasicBlockRange type */
-__hash_namespace_begin
+namespace std {
template <>
struct hash<BasicBlockRange>
{
@@ -68,7 +69,7 @@ struct hash<BasicBlockRange>
return hash<Addr>()(bb.first + bb.second);
}
};
-__hash_namespace_end
+}
class SimPoint : public ProbeListenerObject
{
@@ -109,7 +110,7 @@ class SimPoint : public ProbeListenerObject
};
/** Hash table containing all previously seen basic blocks */
- m5::hash_map<BasicBlockRange, BBInfo> bbMap;
+ std::unordered_map<BasicBlockRange, BBInfo> bbMap;
/** Currently executing basic block */
BasicBlockRange currentBBV;
/** inst count in current basic block */
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index f1cc09e42..a6c7df988 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -272,8 +272,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
public:
- DrainState drain() M5_ATTR_OVERRIDE;
- void drainResume() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
+ void drainResume() override;
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 20acff6ee..631b8ccfc 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -154,8 +154,8 @@ class SimpleThread : public ThreadState
void copyState(ThreadContext *oldContext);
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void startup();
/***************************************************************
diff --git a/src/cpu/testers/rubytest/CheckTable.cc b/src/cpu/testers/rubytest/CheckTable.cc
index decdd20a2..b75fd0a52 100644
--- a/src/cpu/testers/rubytest/CheckTable.cc
+++ b/src/cpu/testers/rubytest/CheckTable.cc
@@ -112,7 +112,7 @@ CheckTable::getCheck(const Addr address)
{
DPRINTF(RubyTest, "Looking for check by address: %s", address);
- m5::hash_map<Addr, Check*>::iterator i = m_lookup_map.find(address);
+ auto i = m_lookup_map.find(address);
if (i == m_lookup_map.end())
return NULL;
diff --git a/src/cpu/testers/rubytest/CheckTable.hh b/src/cpu/testers/rubytest/CheckTable.hh
index fe7109f26..23ca855d7 100644
--- a/src/cpu/testers/rubytest/CheckTable.hh
+++ b/src/cpu/testers/rubytest/CheckTable.hh
@@ -31,9 +31,9 @@
#define __CPU_RUBYTEST_CHECKTABLE_HH__
#include <iostream>
+#include <unordered_map>
#include <vector>
-#include "base/hashmap.hh"
#include "mem/ruby/common/Address.hh"
class Check;
@@ -63,7 +63,7 @@ class CheckTable
CheckTable& operator=(const CheckTable& obj);
std::vector<Check*> m_check_vector;
- m5::hash_map<Addr, Check*> m_lookup_map;
+ std::unordered_map<Addr, Check*> m_lookup_map;
int m_num_writers;
int m_num_readers;
diff --git a/src/cpu/testers/traffic_gen/traffic_gen.hh b/src/cpu/testers/traffic_gen/traffic_gen.hh
index 8b71443f9..e5295bcf5 100644
--- a/src/cpu/testers/traffic_gen/traffic_gen.hh
+++ b/src/cpu/testers/traffic_gen/traffic_gen.hh
@@ -41,7 +41,8 @@
#ifndef __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
#define __CPU_TRAFFIC_GEN_TRAFFIC_GEN_HH__
-#include "base/hashmap.hh"
+#include <unordered_map>
+
#include "base/statistics.hh"
#include "cpu/testers/traffic_gen/generators.hh"
#include "mem/mem_object.hh"
@@ -135,7 +136,7 @@ class TrafficGen : public MemObject
uint32_t currState;
/** Map of generator states */
- m5::hash_map<uint32_t, BaseGen*> states;
+ std::unordered_map<uint32_t, BaseGen*> states;
/** Master port specialisation for the traffic generator */
class TrafficGenPort : public MasterPort
@@ -198,10 +199,10 @@ class TrafficGen : public MemObject
void initState();
- DrainState drain() M5_ATTR_OVERRIDE;
+ DrainState drain() override;
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/** Register statistics */
void regStats();
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index bd471e13a..3a35d444a 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -63,9 +63,9 @@ struct ThreadState : public Serializable {
virtual ~ThreadState();
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void unserialize(CheckpointIn &cp) override;
int cpuId() const { return baseCpu->cpuId(); }
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-16 10:42:35 +0000