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-rw-r--r--src/cpu/o3/commit_impl.hh3
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh1
-rw-r--r--src/cpu/simple/base.cc2
-rw-r--r--src/cpu/simple_thread.cc8
4 files changed, 5 insertions, 9 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index fc24d7edc..9411c6c62 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -642,9 +642,6 @@ DefaultCommit<Impl>::handleInterrupt()
// an interrupt needed to be handled.
DPRINTF(Commit, "Interrupt detected.\n");
- Fault new_interrupt = cpu->getInterrupts();
- assert(new_interrupt != NoFault);
-
// Clear the interrupt now that it's going to be handled
toIEW->commitInfo[0].clearInterrupt = true;
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 44e2cea76..bde4f8079 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -680,7 +680,6 @@ LSQUnit<Impl>::writebackStores()
inst->seqNum);
WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
wb->schedule(curTick + 1);
- delete state;
completeStore(storeWBIdx);
incrStIdx(storeWBIdx);
continue;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 877dc5bd4..4fed2059b 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -79,7 +79,7 @@ BaseSimpleCPU::BaseSimpleCPU(Params *p)
/* asid */ 0);
#endif // !FULL_SYSTEM
- thread->setStatus(ThreadContext::Suspended);
+ thread->setStatus(ThreadContext::Unallocated);
tc = thread->getTC();
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 39f31782b..191ae2f2e 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -221,10 +221,10 @@ SimpleThread::activate(int delay)
lastActivate = curTick;
- if (status() == ThreadContext::Unallocated) {
- cpu->activateWhenReady(tid);
- return;
- }
+// if (status() == ThreadContext::Unallocated) {
+// cpu->activateWhenReady(tid);
+// return;
+// }
_status = ThreadContext::Active;