diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/BaseCPU.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 78b9ae944..51d447f0b 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -144,7 +144,8 @@ class BaseCPU(MemObject): if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: _mem_ports = ["itb.walker.port", "dtb.walker.port", - "interrupts.pio"] + "interrupts.pio", + "interrupts.int_port"] def connectMemPorts(self, bus): for p in self._mem_ports: |