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-rw-r--r--src/cpu/base_dyn_inst.hh1
-rw-r--r--src/cpu/checker/cpu_impl.hh2
-rw-r--r--src/cpu/inorder/cpu.cc10
-rw-r--r--src/cpu/inorder/cpu.hh4
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.cc2
-rw-r--r--src/cpu/inorder/resources/cache_unit.cc2
-rw-r--r--src/cpu/inorder/resources/execution_unit.cc2
-rw-r--r--src/cpu/inorder/resources/mult_div_unit.cc2
-rw-r--r--src/cpu/inorder/resources/tlb_unit.cc2
-rw-r--r--src/cpu/o3/commit_impl.hh2
-rw-r--r--src/cpu/o3/cpu.cc7
-rw-r--r--src/cpu/o3/cpu.hh2
-rw-r--r--src/cpu/o3/dyn_inst_impl.hh2
-rw-r--r--src/cpu/simple/atomic.cc1
-rw-r--r--src/cpu/simple/base.cc2
-rw-r--r--src/cpu/simple/timing.cc1
-rw-r--r--src/cpu/simple_thread.hh7
-rw-r--r--src/cpu/static_inst.hh3
-rw-r--r--src/cpu/thread_context.hh3
-rw-r--r--src/cpu/translation.hh1
20 files changed, 26 insertions, 32 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 41cb13949..e9b7daa4a 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -49,6 +49,7 @@
#include "cpu/static_inst.hh"
#include "cpu/translation.hh"
#include "mem/packet.hh"
+#include "sim/byteswap.hh"
#include "sim/system.hh"
#include "sim/tlb.hh"
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 81f494630..494298cad 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -240,7 +240,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
if (fault != NoFault) {
#if FULL_SYSTEM
- fault->invoke(tc);
+ fault->invoke(tc, curStaticInst);
willChangePC = true;
newPC = thread->readPC();
DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 059996b07..5d4d3c580 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -136,7 +136,7 @@ InOrderCPU::CPUEvent::process()
break;
case Trap:
- cpu->trapCPU(fault, tid);
+ cpu->trapCPU(fault, tid, inst);
break;
default:
@@ -649,16 +649,16 @@ InOrderCPU::updateMemPorts()
#endif
void
-InOrderCPU::trap(Fault fault, ThreadID tid, int delay)
+InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
{
//@ Squash Pipeline during TRAP
- scheduleCpuEvent(Trap, fault, tid, dummyInst[tid], delay);
+ scheduleCpuEvent(Trap, fault, tid, inst, delay);
}
void
-InOrderCPU::trapCPU(Fault fault, ThreadID tid)
+InOrderCPU::trapCPU(Fault fault, ThreadID tid, DynInstPtr inst)
{
- fault->invoke(tcBase(tid));
+ fault->invoke(tcBase(tid), inst->staticInst);
}
void
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 450829e64..abe24d6ed 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -347,8 +347,8 @@ class InOrderCPU : public BaseCPU
/** trap() - sets up a trap event on the cpuTraps to handle given fault.
* trapCPU() - Traps to handle given fault
*/
- void trap(Fault fault, ThreadID tid, int delay = 0);
- void trapCPU(Fault fault, ThreadID tid);
+ void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
+ void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
/** Add Thread to Active Threads List. */
void activateContext(ThreadID tid, int delay = 0);
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index 5486dedee..2465744e5 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -326,7 +326,7 @@ InOrderDynInst::hwrei()
void
InOrderDynInst::trap(Fault fault)
{
- this->cpu->trap(fault, this->threadNumber);
+ this->cpu->trap(fault, this->threadNumber, this);
}
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 67ee51743..73deacb12 100644
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -434,7 +434,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
scheduleEvent(slot_idx, 1);
- cpu->trap(cache_req->fault, tid);
+ cpu->trap(cache_req->fault, tid, inst);
} else {
DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
"to phys. addr:%08p.\n", tid, inst->seqNum,
diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc
index 49ea329cd..91e788fbc 100644
--- a/src/cpu/inorder/resources/execution_unit.cc
+++ b/src/cpu/inorder/resources/execution_unit.cc
@@ -236,7 +236,7 @@ ExecutionUnit::execute(int slot_num)
} else {
warn("inst [sn:%i] had a %s fault",
seq_num, fault->name());
- cpu->trap(fault, tid);
+ cpu->trap(fault, tid, inst);
}
}
}
diff --git a/src/cpu/inorder/resources/mult_div_unit.cc b/src/cpu/inorder/resources/mult_div_unit.cc
index 81e42b2b6..d9a887571 100644
--- a/src/cpu/inorder/resources/mult_div_unit.cc
+++ b/src/cpu/inorder/resources/mult_div_unit.cc
@@ -301,7 +301,7 @@ MultDivUnit::exeMulDiv(int slot_num)
inst->readTid(), inst->readIntResult(0));
} else {
warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
- cpu->trap(fault, tid);
+ cpu->trap(fault, tid, inst);
}
}
diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc
index 0410d6b24..59840d15b 100644
--- a/src/cpu/inorder/resources/tlb_unit.cc
+++ b/src/cpu/inorder/resources/tlb_unit.cc
@@ -176,7 +176,7 @@ TLBUnit::execute(int slot_idx)
scheduleEvent(slot_idx, 1);
// Let CPU handle the fault
- cpu->trap(tlb_req->fault, tid);
+ cpu->trap(tlb_req->fault, tid, inst);
}
} else {
DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index cb5f23814..468781e4d 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1068,7 +1068,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
// needed to update the state as soon as possible. This
// prevents external agents from changing any specific state
// that the trap need.
- cpu->trap(inst_fault, tid);
+ cpu->trap(inst_fault, tid, head_inst);
// Exit state update mode to avoid accidental updating.
thread[tid]->inSyscall = false;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 49bfe88e3..7eea04ce6 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -926,7 +926,8 @@ FullO3CPU<Impl>::processInterrupts(Fault interrupt)
this->interrupts->updateIntrInfo(this->threadContexts[0]);
DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
- this->trap(interrupt, 0);
+ DynInstPtr dummyInst;
+ this->trap(interrupt, 0, dummyInst);
}
template <class Impl>
@@ -943,10 +944,10 @@ FullO3CPU<Impl>::updateMemPorts()
template <class Impl>
void
-FullO3CPU<Impl>::trap(Fault fault, ThreadID tid)
+FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, DynInstPtr inst)
{
// Pass the thread's TC into the invoke method.
- fault->invoke(this->threadContexts[tid]);
+ fault->invoke(this->threadContexts[tid], inst->staticInst);
}
#if !FULL_SYSTEM
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index a102a21f5..e7368993b 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -367,7 +367,7 @@ class FullO3CPU : public BaseO3CPU
{ return globalSeqNum++; }
/** Traps to handle given fault. */
- void trap(Fault fault, ThreadID tid);
+ void trap(Fault fault, ThreadID tid, DynInstPtr inst);
#if FULL_SYSTEM
/** HW return from error interrupt. */
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 8d391ceaf..9406e2be0 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -155,7 +155,7 @@ template <class Impl>
void
BaseO3DynInst<Impl>::trap(Fault fault)
{
- this->cpu->trap(fault, this->threadNumber);
+ this->cpu->trap(fault, this->threadNumber, this);
}
template <class Impl>
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 1726db193..d97e7aeec 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -38,6 +38,7 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/AtomicSimpleCPU.hh"
+#include "sim/faults.hh"
#include "sim/system.hh"
using namespace std;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index d7fc81de6..98feb8bf5 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -506,7 +506,7 @@ BaseSimpleCPU::advancePC(Fault fault)
fetchOffset = 0;
if (fault != NoFault) {
curMacroStaticInst = StaticInst::nullStaticInstPtr;
- fault->invoke(tc);
+ fault->invoke(tc, curStaticInst);
predecoder.reset();
} else {
//If we're at the last micro op for this instruction
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 4b093e115..7b45822d6 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -38,6 +38,7 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "params/TimingSimpleCPU.hh"
+#include "sim/faults.hh"
#include "sim/system.hh"
using namespace std;
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 1fbb2ab5a..e4a7b7a77 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -241,13 +241,6 @@ class SimpleThread : public ThreadState
virtual bool misspeculating();
- Fault instRead(RequestPtr &req)
- {
- panic("instRead not implemented");
- // return funcPhysMem->read(req, inst);
- return NoFault;
- }
-
void copyArchRegs(ThreadContext *tc);
void clearArchRegs()
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index fa4205836..0ae8653c5 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -43,8 +43,7 @@
#include "base/refcnt.hh"
#include "base/types.hh"
#include "cpu/op_class.hh"
-#include "sim/faults.hh"
-#include "sim/faults.hh"
+#include "sim/fault.hh"
// forward declarations
struct AlphaSimpleImpl;
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 7f6d258ab..84ef57922 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -36,9 +36,6 @@
#include "base/types.hh"
#include "config/full_system.hh"
#include "config/the_isa.hh"
-#include "mem/request.hh"
-#include "sim/byteswap.hh"
-#include "sim/faults.hh"
#include "sim/serialize.hh"
// @todo: Figure out a more architecture independent way to obtain the ITB and
diff --git a/src/cpu/translation.hh b/src/cpu/translation.hh
index 983a748cf..7db7c381a 100644
--- a/src/cpu/translation.hh
+++ b/src/cpu/translation.hh
@@ -33,6 +33,7 @@
#ifndef __CPU_TRANSLATION_HH__
#define __CPU_TRANSLATION_HH__
+#include "sim/faults.hh"
#include "sim/tlb.hh"
/**
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-25 05:18:04 +0000