summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/base.cc2
-rw-r--r--src/cpu/base.hh4
-rw-r--r--src/cpu/exetrace.cc55
-rw-r--r--src/cpu/m5legion_interface.h4
-rw-r--r--src/cpu/memtest/memtest.hh2
-rw-r--r--src/cpu/o3/fetch.hh2
-rw-r--r--src/cpu/o3/iew_impl.hh18
-rw-r--r--src/cpu/o3/lsq.hh2
-rw-r--r--src/cpu/ozone/front_end.hh2
-rw-r--r--src/cpu/ozone/lw_lsq.hh2
-rw-r--r--src/cpu/simple/atomic.cc33
-rw-r--r--src/cpu/simple/atomic.hh2
-rw-r--r--src/cpu/simple/timing.hh2
13 files changed, 96 insertions, 34 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 7cbbb0b96..31604ad58 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -96,7 +96,7 @@ CPUProgressEvent::description()
#if FULL_SYSTEM
BaseCPU::BaseCPU(Params *p)
- : MemObject(p->name), clock(p->clock), checkInterrupts(true),
+ : MemObject(p->name), clock(p->clock), instCnt(0), checkInterrupts(true),
params(p), number_of_threads(p->numberOfThreads), system(p->system),
phase(p->phase)
#else
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 1d9b6a93b..8c6b079da 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -70,12 +70,16 @@ class BaseCPU : public MemObject
protected:
// CPU's clock period in terms of the number of ticks of curTime.
Tick clock;
+ // @todo remove me after debugging with legion done
+ Tick instCnt;
public:
// Tick currentTick;
inline Tick frequency() const { return Clock::Frequency / clock; }
inline Tick cycles(int numCycles) const { return clock * numCycles; }
inline Tick curCycle() const { return curTick / clock; }
+ // @todo remove me after debugging with legion done
+ Tick instCount() { return instCnt; }
/** The next cycle the CPU should be scheduled, given a cache
* access or quiesce event returning on this cycle. This function
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 780a0c4f7..98e75d83a 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -57,6 +57,10 @@
using namespace std;
using namespace TheISA;
+#if THE_ISA == SPARC_ISA && FULL_SYSTEM
+static int diffcount = 0;
+#endif
+
namespace Trace {
SharedData *shared_data = NULL;
}
@@ -281,12 +285,13 @@ Trace::InstRecord::dump(ostream &outs)
//
outs << endl;
}
-#if THE_ISA == SPARC_ISA
+#if THE_ISA == SPARC_ISA && FULL_SYSTEM
// Compare
if (flags[LEGION_LOCKSTEP])
{
bool compared = false;
bool diffPC = false;
+ bool diffCC = false;
bool diffInst = false;
bool diffRegs = false;
bool diffTpc = false;
@@ -319,6 +324,11 @@ Trace::InstRecord::dump(ostream &outs)
lgnPc = shared_data->pc & TheISA::PAddrImplMask;
if (lgnPc != m5Pc)
diffPC = true;
+
+ if (shared_data->cycle_count !=
+ thread->getCpuPtr()->instCount())
+ diffCC = true;
+
if (shared_data->instruction !=
(SparcISA::MachInst)staticInst->machInst) {
diffInst = true;
@@ -334,19 +344,19 @@ Trace::InstRecord::dump(ostream &outs)
for (int i = 1; i <= MaxTL; i++) {
thread->setMiscReg(MISCREG_TL, i);
if (thread->readMiscReg(MISCREG_TPC) !=
- shared_data->tpc[i])
+ shared_data->tpc[i-1])
diffTpc = true;
if (thread->readMiscReg(MISCREG_TNPC) !=
- shared_data->tnpc[i])
+ shared_data->tnpc[i-1])
diffTnpc = true;
if (thread->readMiscReg(MISCREG_TSTATE) !=
- shared_data->tstate[i])
+ shared_data->tstate[i-1])
diffTstate = true;
if (thread->readMiscReg(MISCREG_TT) !=
- shared_data->tt[i])
+ shared_data->tt[i-1])
diffTt = true;
if (thread->readMiscReg(MISCREG_HTSTATE) !=
- shared_data->htstate[i])
+ shared_data->htstate[i-1])
diffHtstate = true;
}
thread->setMiscReg(MISCREG_TL, oldTl);
@@ -399,15 +409,18 @@ Trace::InstRecord::dump(ostream &outs)
thread->readMiscReg(NumIntArchRegs + 6))
diffCleanwin = true;
- if (diffPC || diffInst || diffRegs || diffTpc || diffTnpc ||
- diffTstate || diffTt || diffHpstate ||
+ if ((diffPC || diffCC || diffInst || diffRegs || diffTpc ||
+ diffTnpc || diffTstate || diffTt || diffHpstate ||
diffHtstate || diffHtba || diffPstate || diffY ||
diffCcr || diffTl || diffGl || diffAsi || diffPil ||
diffCwp || diffCansave || diffCanrestore ||
- diffOtherwin || diffCleanwin) {
+ diffOtherwin || diffCleanwin)
+ && !((staticInst->machInst & 0xC1F80000) == 0x81D00000)) {
outs << "Differences found between M5 and Legion:";
if (diffPC)
outs << " [PC]";
+ if (diffCC)
+ outs << " [CC]";
if (diffInst)
outs << " [Instruction]";
if (diffRegs)
@@ -459,6 +472,13 @@ Trace::InstRecord::dump(ostream &outs)
<< "Legion PC: " << "0x"<< setw(16) << setfill('0') << hex
<< lgnPc << endl << endl;
+ outs << right << setfill(' ') << setw(15)
+ << "M5 CC: " << "0x"<< setw(16) << setfill('0')
+ << hex << thread->getCpuPtr()->instCount() << endl;
+ outs << setfill(' ') << setw(15)
+ << "Legion CC: " << "0x"<< setw(16) << setfill('0') << hex
+ << shared_data->cycle_count << endl << endl;
+
outs << setfill(' ') << setw(15)
<< "M5 Inst: " << "0x"<< setw(8)
<< setfill('0') << hex << staticInst->machInst
@@ -532,19 +552,19 @@ Trace::InstRecord::dump(ostream &outs)
thread->setMiscReg(MISCREG_TL, i);
printRegPair(outs, "Tpc",
thread->readMiscReg(MISCREG_TPC),
- shared_data->tpc[i]);
+ shared_data->tpc[i-1]);
printRegPair(outs, "Tnpc",
thread->readMiscReg(MISCREG_TNPC),
- shared_data->tnpc[i]);
+ shared_data->tnpc[i-1]);
printRegPair(outs, "Tstate",
thread->readMiscReg(MISCREG_TSTATE),
- shared_data->tstate[i]);
+ shared_data->tstate[i-1]);
printRegPair(outs, "Tt",
thread->readMiscReg(MISCREG_TT),
- shared_data->tt[i]);
+ shared_data->tt[i-1]);
printRegPair(outs, "Htstate",
thread->readMiscReg(MISCREG_HTSTATE),
- shared_data->htstate[i]);
+ shared_data->htstate[i-1]);
}
thread->setMiscReg(MISCREG_TL, oldTl);
outs << endl;
@@ -573,7 +593,12 @@ Trace::InstRecord::dump(ostream &outs)
<< endl;*/
}
}
- fatal("Differences found between Legion and M5\n");
+ thread->getITBPtr()->dumpAll();
+ thread->getDTBPtr()->dumpAll();
+
+ diffcount++;
+ if (diffcount > 2)
+ fatal("Differences found between Legion and M5\n");
}
compared = true;
diff --git a/src/cpu/m5legion_interface.h b/src/cpu/m5legion_interface.h
index 373fbeb11..bfb88485a 100644
--- a/src/cpu/m5legion_interface.h
+++ b/src/cpu/m5legion_interface.h
@@ -30,7 +30,7 @@
#include <unistd.h>
-#define VERSION 0xA1000005
+#define VERSION 0xA1000006
#define OWN_M5 0x000000AA
#define OWN_LEGION 0x00000055
@@ -42,6 +42,8 @@ typedef struct {
uint64_t pc;
uint64_t new_pc;
+ uint64_t cycle_count;
+ uint64_t new_cycle_count;
uint32_t instruction;
uint32_t new_instruction;
uint64_t intregs[32];
diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index 7bf34d827..264309fd7 100644
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -116,7 +116,7 @@ class MemTest : public MemObject
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
+ { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
};
CpuPort cachePort;
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 4f5a161e0..0371cd2bc 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -98,7 +98,7 @@ class DefaultFetch
/** Returns the address ranges of this device. */
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
+ { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
/** Timing version of receive. Handles setting fetch to the
* proper status to start fetching. */
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 24c8484b4..70200d648 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -528,6 +528,7 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid)
#if ISA_HAS_DELAY_SLOT
toCommit->nextNPC[tid] = inst->readNextNPC();
#endif
+ toCommit->branchMispredict[tid] = false;
toCommit->includeSquashInst[tid] = false;
@@ -547,6 +548,7 @@ DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid)
#if ISA_HAS_DELAY_SLOT
toCommit->nextNPC[tid] = inst->readNextNPC();
#endif
+ toCommit->branchMispredict[tid] = false;
// Must include the broadcasted SN in the squash.
toCommit->includeSquashInst[tid] = true;
@@ -1308,7 +1310,8 @@ DefaultIEW<Impl>::executeInsts()
} else if (fault != NoFault) {
// If the instruction faulted, then we need to send it along to commit
// without the instruction completing.
- DPRINTF(IEW, "Store has fault! [sn:%lli]\n", inst->seqNum);
+ DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
+ fault->name(), inst->seqNum);
// Send this instruction to commit, also make sure iew stage
// realizes there is activity.
@@ -1345,7 +1348,8 @@ DefaultIEW<Impl>::executeInsts()
// instruction first, so the branch resolution order will be correct.
unsigned tid = inst->threadNumber;
- if (!fetchRedirect[tid]) {
+ if (!fetchRedirect[tid] ||
+ toCommit->squashedSeqNum[tid] > inst->seqNum) {
if (inst->mispredicted()) {
fetchRedirect[tid] = true;
@@ -1368,8 +1372,6 @@ DefaultIEW<Impl>::executeInsts()
predictedNotTakenIncorrect++;
}
} else if (ldstQueue.violation(tid)) {
- fetchRedirect[tid] = true;
-
// If there was an ordering violation, then get the
// DynInst that caused the violation. Note that this
// clears the violation signal.
@@ -1380,6 +1382,14 @@ DefaultIEW<Impl>::executeInsts()
"%#x, inst PC: %#x. Addr is: %#x.\n",
violator->readPC(), inst->readPC(), inst->physEffAddr);
+ // Ensure the violating instruction is older than
+ // current squash
+ if (fetchRedirect[tid] &&
+ violator->seqNum >= toCommit->squashedSeqNum[tid])
+ continue;
+
+ fetchRedirect[tid] = true;
+
// Tell the instruction queue that a violation has occured.
instQueue.violation(inst, violator);
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 7559a36d5..e68085cfd 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -313,7 +313,7 @@ class LSQ {
/** Returns the address ranges of this device. */
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
+ { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
/** Timing version of receive. Handles writing back and
* completing the load or store that has returned from
diff --git a/src/cpu/ozone/front_end.hh b/src/cpu/ozone/front_end.hh
index e09e4de9c..0acf99ead 100644
--- a/src/cpu/ozone/front_end.hh
+++ b/src/cpu/ozone/front_end.hh
@@ -92,7 +92,7 @@ class FrontEnd
/** Returns the address ranges of this device. */
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
+ { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
/** Timing version of receive. Handles setting fetch to the
* proper status to start fetching. */
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index 7e6849668..c981b8e63 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -258,7 +258,7 @@ class OzoneLWLSQ {
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
+ { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
virtual bool recvTiming(PacketPtr pkt);
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 8cfe2ee83..8db864153 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -29,6 +29,7 @@
*/
#include "arch/locked_mem.hh"
+#include "arch/mmaped_ipr.hh"
#include "arch/utility.hh"
#include "cpu/exetrace.hh"
#include "cpu/simple/atomic.hh"
@@ -289,10 +290,16 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
if (fault == NoFault) {
pkt->reinitFromRequest();
- dcache_latency = dcachePort.sendAtomic(pkt);
+ if (req->isMmapedIpr())
+ dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
+ else
+ dcache_latency = dcachePort.sendAtomic(pkt);
dcache_access = true;
-
- assert(pkt->result == Packet::Success);
+#if !defined(NDEBUG)
+ if (pkt->result != Packet::Success)
+ panic("Unable to find responder for address pa = %#X va = %#X\n",
+ pkt->req->getPaddr(), pkt->req->getVaddr());
+#endif
data = pkt->get<T>();
if (req->isLocked()) {
@@ -376,14 +383,22 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
}
if (do_access) {
- data = htog(data);
pkt->reinitFromRequest();
pkt->dataStatic(&data);
- dcache_latency = dcachePort.sendAtomic(pkt);
+ if (req->isMmapedIpr()) {
+ dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
+ } else {
+ data = htog(data);
+ dcache_latency = dcachePort.sendAtomic(pkt);
+ }
dcache_access = true;
- assert(pkt->result == Packet::Success);
+#if !defined(NDEBUG)
+ if (pkt->result != Packet::Success)
+ panic("Unable to find responder for address pa = %#X va = %#X\n",
+ pkt->req->getPaddr(), pkt->req->getVaddr());
+#endif
}
if (req->isLocked()) {
@@ -476,9 +491,15 @@ AtomicSimpleCPU::tick()
dcache_access = false; // assume no dcache access
preExecute();
+
fault = curStaticInst->execute(this, traceData);
postExecute();
+ // @todo remove me after debugging with legion done
+ if (curStaticInst && (!curStaticInst->isMicroOp() ||
+ curStaticInst->isLastMicroOp()))
+ instCnt++;
+
if (simulate_stalls) {
Tick icache_stall = icache_latency - cycles(1);
Tick dcache_stall =
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 0df6fe079..42c7bf23a 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -106,7 +106,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
+ { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
};
CpuPort icachePort;
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index fe5d03666..abcb224bf 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -94,7 +94,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
- { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
+ { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
struct TickEvent : public Event
{
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-20 04:19:30 +0000