diff options
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 60 | ||||
-rw-r--r-- | src/cpu/inorder/resources/fetch_unit.cc | 21 | ||||
-rw-r--r-- | src/cpu/inorder/resources/fetch_unit.hh | 2 | ||||
-rw-r--r-- | src/cpu/inorder/resources/graduation_unit.cc | 2 |
4 files changed, 21 insertions, 64 deletions
diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index c627466a1..ee7ec8212 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -159,8 +159,7 @@ int CacheUnit::getSlot(DynInstPtr inst) { ThreadID tid = inst->readTid(); - - if (tlbBlocked[inst->threadNumber]) { + if (tlbBlocked[tid]) { return -1; } @@ -171,40 +170,11 @@ CacheUnit::getSlot(DynInstPtr inst) "cache access\n", inst->readTid(), inst->seqNum); } - Addr req_addr = inst->getMemAddr(); - - if (resName == "icache_port" || - find(addrList[tid].begin(), addrList[tid].end(), req_addr) == - addrList[tid].end()) { - - int new_slot = Resource::getSlot(inst); - - if (new_slot == -1) - return -1; - - inst->memTime = curTick(); - setAddrDependency(inst); - return new_slot; - } else { - // Allow same instruction multiple accesses to same address - // should only happen maybe after a squashed inst. needs to replay - if (addrMap[tid][req_addr] == inst->seqNum) { - int new_slot = Resource::getSlot(inst); - - if (new_slot == -1) - return -1; - - return new_slot; - } else { - DPRINTF(InOrderCachePort, - "[tid:%i] Denying request because there is an outstanding" - " request to/for addr. %08p. by [sn:%i] @ tick %i\n", - inst->readTid(), req_addr, addrMap[tid][req_addr], inst->memTime); - return -1; - } - } - - return -1; + int new_slot = Resource::getSlot(inst); + inst->memTime = curTick(); + //@note: add back in if you want speculative loads/store capability + //setAddrDependency(inst); + return new_slot; } void @@ -758,6 +728,14 @@ CacheUnit::execute(int slot_num) DPRINTF(InOrderCachePort, "[tid:%i]: [sn:%i]: Trying to Complete Data Write Access\n", tid, inst->seqNum); + DPRINTF(InOrderCachePort, + "[tid:%i]: [sn:%i]: cSwap:%i LLSC:%i isSwap:%i isCond:%i\n", + tid, inst->seqNum, + cache_req->memReq->isCondSwap(), + cache_req->memReq->isLLSC(), + cache_req->memReq->isSwap(), + inst->isStoreConditional()); + //@todo: check that timing translation is finished here if (cache_req->dataPkt->isRead()) { assert(cache_req->memReq->isCondSwap() || @@ -824,7 +802,8 @@ CacheUnit::execute(int slot_num) void CacheUnit::finishCacheUnitReq(DynInstPtr inst, CacheRequest *cache_req) { - removeAddrDependency(inst); + //@note: add back in for speculative load/store capability + //removeAddrDependency(inst); cache_req->setMemStall(false); cache_req->done(); } @@ -1219,10 +1198,11 @@ void CacheUnit::squashCacheRequest(CacheReqPtr req_ptr) { DynInstPtr inst = req_ptr->getInst(); - req_ptr->setSquashed(); inst->setSquashed(); - if (inst->validMemAddr()) { + + //@note: add back in for speculative load/store capability + /*if (inst->validMemAddr()) { DPRINTF(AddrDep, "Squash of [tid:%i] [sn:%i], attempting to " "remove addr. %08p dependencies.\n", inst->readTid(), @@ -1230,7 +1210,7 @@ CacheUnit::squashCacheRequest(CacheReqPtr req_ptr) inst->getMemAddr()); removeAddrDependency(inst); - } + }*/ } diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc index 52997917d..28200c852 100644 --- a/src/cpu/inorder/resources/fetch_unit.cc +++ b/src/cpu/inorder/resources/fetch_unit.cc @@ -118,27 +118,6 @@ FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it, inst->setMachInst(ext_inst); } -int -FetchUnit::getSlot(DynInstPtr inst) -{ - if (tlbBlocked[inst->threadNumber]) { - return -1; - } - - if (!inst->validMemAddr()) { - panic("[tid:%i][sn:%i] Mem. Addr. must be set before requesting " - "cache access\n", inst->readTid(), inst->seqNum); - } - - int new_slot = Resource::getSlot(inst); - - if (new_slot == -1) - return -1; - - inst->memTime = curTick(); - return new_slot; -} - void FetchUnit::removeAddrDependency(DynInstPtr inst) { diff --git a/src/cpu/inorder/resources/fetch_unit.hh b/src/cpu/inorder/resources/fetch_unit.hh index cc1e72914..6c0b4871b 100644 --- a/src/cpu/inorder/resources/fetch_unit.hh +++ b/src/cpu/inorder/resources/fetch_unit.hh @@ -83,8 +83,6 @@ class FetchUnit : public CacheUnit int res_idx, int slot_num, unsigned cmd); - int getSlot(DynInstPtr inst); - /** Executes one of the commands from the "Command" enum */ void execute(int slot_num); diff --git a/src/cpu/inorder/resources/graduation_unit.cc b/src/cpu/inorder/resources/graduation_unit.cc index d34e1b512..afa9421a8 100644 --- a/src/cpu/inorder/resources/graduation_unit.cc +++ b/src/cpu/inorder/resources/graduation_unit.cc @@ -88,7 +88,7 @@ GraduationUnit::execute(int slot_num) DPRINTF(InOrderGraduation, "[tid:%i]:[sn:%i]: Graduating instruction %s.\n", - tid, inst->seqNum, inst->instName()); + tid, inst->seqNum, inst->staticInst->disassemble(inst->instAddr())); // Release Non-Speculative "Block" on instructions that could not // execute because there was a non-speculative inst. active. |