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-rw-r--r--src/cpu/checker/cpu_impl.hh5
-rw-r--r--src/cpu/o3/fetch_impl.hh6
-rw-r--r--src/cpu/ozone/front_end_impl.hh4
-rw-r--r--src/cpu/simple/base.cc4
-rw-r--r--src/cpu/simple_thread.cc30
-rw-r--r--src/cpu/simple_thread.hh2
-rw-r--r--src/cpu/thread_state.cc31
-rw-r--r--src/cpu/thread_state.hh9
8 files changed, 58 insertions, 33 deletions
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 36c7349e6..56e13dd1e 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -199,8 +199,13 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
// Checks both the machine instruction and the PC.
validateInst(inst);
+#if THE_ISA == ALPHA_ISA
+ curStaticInst = StaticInst::decode(makeExtMI(machInst,
+ thread->readPC()));
+#elif THE_ISA == SPARC_ISA
curStaticInst = StaticInst::decode(makeExtMI(machInst,
thread->getTC()));
+#endif
#if FULL_SYSTEM
thread->setInst(machInst);
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 2b152e376..31f3b96d6 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1117,7 +1117,11 @@ DefaultFetch<Impl>::fetch(bool &status_change)
inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
(&cacheData[tid][offset]));
- ext_inst = TheISA::makeExtMI(inst, cpu->tcBase(tid));
+#if THE_ISA == ALPHA_ISA
+ ext_inst = TheISA::makeExtMI(inst, fetch_PC);
+#elif THE_ISA == SPARC_ISA
+ ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
+#endif
// Create a new DynInst from the instruction fetched.
DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 63cf0a952..6d02c58cb 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -882,7 +882,11 @@ FrontEnd<Impl>::getInstFromCacheline()
// Get the instruction from the array of the cache line.
inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset]));
+#if THE_ISA == ALPHA_ISA
+ ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC);
+#elif THE_ISA == SPARC_ISA
ExtMachInst decode_inst = TheISA::makeExtMI(inst, tc);
+#endif
// Create a new DynInst from the instruction fetched.
DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst),
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 47b3b938f..6a2c0bbe9 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -398,7 +398,11 @@ BaseSimpleCPU::preExecute()
inst = gtoh(inst);
//If we're not in the middle of a macro instruction
if (!curMacroStaticInst) {
+#if THE_ISA == ALPHA_ISA
+ StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->readPC()));
+#elif THE_ISA == SPARC_ISA
StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
+#endif
if (instPtr->isMacroOp()) {
curMacroStaticInst = instPtr;
curStaticInst = curMacroStaticInst->
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index d4e5f8230..8bb4ec46b 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -129,6 +129,10 @@ SimpleThread::SimpleThread()
SimpleThread::~SimpleThread()
{
+#if FULL_SYSTEM
+ delete physPort;
+ delete virtPort;
+#endif
delete tc;
}
@@ -304,11 +308,9 @@ SimpleThread::getVirtPort(ThreadContext *src_tc)
if (!src_tc)
return virtPort;
- VirtualPort *vp;
- Port *mem_port;
+ VirtualPort *vp = new VirtualPort("tc-vport", src_tc);
+ Port *mem_port = getMemFuncPort();
- vp = new VirtualPort("tc-vport", src_tc);
- mem_port = system->physmem->getPort("functional");
mem_port->setPeer(vp);
vp->setPeer(mem_port);
return vp;
@@ -323,25 +325,5 @@ SimpleThread::delVirtPort(VirtualPort *vp)
}
}
-#else
-TranslatingPort *
-SimpleThread::getMemPort()
-{
- if (port != NULL)
- return port;
-
- /* Use this port to for syscall emulation writes to memory. */
- Port *dcache_port;
- port = new TranslatingPort(csprintf("%s-%d-funcport",
- cpu->name(), tid),
- process->pTable, false);
- dcache_port = cpu->getPort("dcache_port");
- assert(dcache_port != NULL);
- dcache_port = dcache_port->getPeer();
-// mem_port->setPeer(port);
- port->setPeer(dcache_port);
- return port;
-}
-
#endif
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index b654c130e..9a575f06b 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -171,8 +171,6 @@ class SimpleThread : public ThreadState
bool simPalCheck(int palFunc);
#else
- // Override this function.
- TranslatingPort *getMemPort();
Fault translateInstReq(RequestPtr &req)
{
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index f81b78147..a6fff5fc3 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -59,6 +59,16 @@ ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
numLoad = 0;
}
+ThreadState::~ThreadState()
+{
+#if !FULL_SYSTEM
+ if (port) {
+ delete port->getPeer();
+ delete port;
+ }
+#endif
+}
+
void
ThreadState::serialize(std::ostream &os)
{
@@ -124,11 +134,24 @@ ThreadState::getMemPort()
return port;
/* Use this port to for syscall emulation writes to memory. */
- Port *dcache_port, *func_mem_port;
port = new TranslatingPort(csprintf("%s-%d-funcport",
baseCpu->name(), tid),
process->pTable, false);
+ Port *func_port = getMemFuncPort();
+
+ func_port->setPeer(port);
+ port->setPeer(func_port);
+
+ return port;
+}
+#endif
+
+Port *
+ThreadState::getMemFuncPort()
+{
+ Port *dcache_port, *func_mem_port;
+
dcache_port = baseCpu->getPort("dcache_port");
assert(dcache_port != NULL);
@@ -138,9 +161,5 @@ ThreadState::getMemPort()
func_mem_port = mem_object->getPort("functional");
assert(func_mem_port != NULL);
- func_mem_port->setPeer(port);
- port->setPeer(func_mem_port);
-
- return port;
+ return func_mem_port;
}
-#endif
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 14673aabb..862d671f2 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -51,6 +51,7 @@ namespace Kernel {
class BaseCPU;
class Checkpoint;
+class Port;
class TranslatingPort;
/**
@@ -69,6 +70,8 @@ struct ThreadState {
short _asid);
#endif
+ ~ThreadState();
+
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
@@ -136,6 +139,12 @@ struct ThreadState {
/** Sets the status of this thread. */
void setStatus(Status new_status) { _status = new_status; }
+ protected:
+ /** Gets a functional port from the memory object that's connected
+ * to the CPU. */
+ Port *getMemFuncPort();
+
+ public:
/** Number of instructions committed. */
Counter numInst;
/** Stat for number instructions committed. */
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 09:10:58 +0000