diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/o3/commit.hh | 2 | ||||
| -rw-r--r-- | src/cpu/o3/commit_impl.hh | 3 | ||||
| -rw-r--r-- | src/cpu/o3/cpu.cc | 1 | ||||
| -rw-r--r-- | src/cpu/o3/fetch.hh | 2 | ||||
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 9 | ||||
| -rw-r--r-- | src/cpu/o3/iew.hh | 4 | ||||
| -rw-r--r-- | src/cpu/o3/iew_impl.hh | 19 | ||||
| -rw-r--r-- | src/cpu/o3/rename.hh | 15 | ||||
| -rw-r--r-- | src/cpu/o3/rename_impl.hh | 19 |
9 files changed, 73 insertions, 1 deletions
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index 6688a70dc..48c169389 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -154,6 +154,8 @@ class DefaultCommit /** Probe Points. */ ProbePointArg<DynInstPtr> *ppCommit; ProbePointArg<DynInstPtr> *ppCommitStall; + /** To probe when an instruction is squashed */ + ProbePointArg<DynInstPtr> *ppSquash; public: /** Construct a DefaultCommit with the given parameters. */ diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 5323e1413..c6c6ea723 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -173,6 +173,7 @@ DefaultCommit<Impl>::regProbePoints() { ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit"); ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall"); + ppSquash = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Squash"); } template <class Impl> @@ -1010,6 +1011,8 @@ DefaultCommit<Impl>::commitInsts() rob->retireHead(commit_thread); ++commitSquashedInsts; + // Notify potential listeners that this instruction is squashed + ppSquash->notify(head_inst); // Record that the number of ROB entries has changed. changedROBNumEntries[tid] = true; diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 665654f68..694762167 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -416,6 +416,7 @@ FullO3CPU<Impl>::regProbePoints() ppDataAccessComplete = new ProbePointArg<std::pair<DynInstPtr, PacketPtr> >(getProbeManager(), "DataAccessComplete"); fetch.regProbePoints(); + rename.regProbePoints(); iew.regProbePoints(); commit.regProbePoints(); } diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 536568bc2..672fb499b 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -197,6 +197,8 @@ class DefaultFetch /** Probe points. */ ProbePointArg<DynInstPtr> *ppFetch; + /** To probe when a fetch request is successfully sent. */ + ProbePointArg<RequestPtr> *ppFetchRequestSent; public: /** DefaultFetch constructor. */ diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index cb123afd2..4b1479bcb 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -171,6 +171,9 @@ void DefaultFetch<Impl>::regProbePoints() { ppFetch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Fetch"); + ppFetchRequestSent = new ProbePointArg<RequestPtr>(cpu->getProbeManager(), + "FetchRequest"); + } template <class Impl> @@ -695,6 +698,9 @@ DefaultFetch<Impl>::finishTranslation(const Fault &fault, RequestPtr mem_req) "response.\n", tid); lastIcacheStall[tid] = curTick(); fetchStatus[tid] = IcacheWaitResponse; + // Notify Fetch Request probe when a packet containing a fetch + // request is successfully sent + ppFetchRequestSent->notify(mem_req); } } else { // Don't send an instruction to decode if we can't handle it. @@ -1422,6 +1428,9 @@ DefaultFetch<Impl>::recvReqRetry() if (cpu->getInstPort().sendTimingReq(retryPkt)) { fetchStatus[retryTid] = IcacheWaitResponse; + // Notify Fetch Request probe when a retryPkt is successfully sent. + // Note that notify must be called before retryPkt is set to NULL. + ppFetchRequestSent->notify(retryPkt->req); retryPkt = NULL; retryTid = InvalidThreadID; cacheBlocked = false; diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh index 957a085ae..de8834005 100644 --- a/src/cpu/o3/iew.hh +++ b/src/cpu/o3/iew.hh @@ -126,6 +126,10 @@ class DefaultIEW /** Probe points. */ ProbePointArg<DynInstPtr> *ppMispredict; ProbePointArg<DynInstPtr> *ppDispatch; + /** To probe when instruction execution begins. */ + ProbePointArg<DynInstPtr> *ppExecute; + /** To probe when instruction execution is complete. */ + ProbePointArg<DynInstPtr> *ppToCommit; public: /** Constructs a DefaultIEW with the given parameters. */ diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index ae76aa9e1..e02429b14 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -125,6 +125,18 @@ DefaultIEW<Impl>::regProbePoints() { ppDispatch = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Dispatch"); ppMispredict = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Mispredict"); + /** + * Probe point with dynamic instruction as the argument used to probe when + * an instruction starts to execute. + */ + ppExecute = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), + "Execute"); + /** + * Probe point with dynamic instruction as the argument used to probe when + * an instruction execution completes and it is marked ready to commit. + */ + ppToCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), + "ToCommit"); } template <class Impl> @@ -1190,6 +1202,10 @@ DefaultIEW<Impl>::executeInsts() DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", inst->pcState(), inst->threadNumber,inst->seqNum); + // Notify potential listeners that this instruction has started + // executing + ppExecute->notify(inst); + // Check if the instruction is squashed; if so then skip it if (inst->isSquashed()) { DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" @@ -1402,6 +1418,9 @@ DefaultIEW<Impl>::writebackInsts() inst->seqNum, inst->pcState()); iewInstsToCommit[tid]++; + // Notify potential listeners that execution is complete for this + // instruction. + ppToCommit->notify(inst); // Some instructions will be sent to commit without having // executed because they need commit to handle them. diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh index a543cefb8..f8becc114 100644 --- a/src/cpu/o3/rename.hh +++ b/src/cpu/o3/rename.hh @@ -45,10 +45,12 @@ #define __CPU_O3_RENAME_HH__ #include <list> +#include <utility> #include "base/statistics.hh" #include "config/the_isa.hh" #include "cpu/timebuf.hh" +#include "sim/probe/probe.hh" struct DerivO3CPUParams; @@ -119,6 +121,16 @@ class DefaultRename /** Per-thread status. */ ThreadStatus renameStatus[Impl::MaxThreads]; + /** Probe points. */ + typedef typename std::pair<InstSeqNum, short int> SeqNumRegPair; + /** To probe when register renaming for an instruction is complete */ + ProbePointArg<DynInstPtr> *ppRename; + /** + * To probe when an instruction is squashed and the register mapping + * for it needs to be undone + */ + ProbePointArg<SeqNumRegPair> *ppSquashInRename; + public: /** DefaultRename constructor. */ DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params); @@ -129,6 +141,9 @@ class DefaultRename /** Registers statistics. */ void regStats(); + /** Registers probes. */ + void regProbePoints(); + /** Sets the main backwards communication time buffer pointer. */ void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 43b7ba9aa..b19b3414c 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -186,6 +186,15 @@ DefaultRename<Impl>::regStats() template <class Impl> void +DefaultRename<Impl>::regProbePoints() +{ + ppRename = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Rename"); + ppSquashInRename = new ProbePointArg<SeqNumRegPair>(cpu->getProbeManager(), + "SquashInRename"); +} + +template <class Impl> +void DefaultRename<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) { timeBuffer = tb_ptr; @@ -697,7 +706,9 @@ DefaultRename<Impl>::renameInsts(ThreadID tid) storesInProgress[tid]++; } ++renamed_insts; - + // Notify potential listeners that source and destination registers for + // this instruction have been renamed. + ppRename->notify(inst); // Put instruction in rename queue. toIEW->insts[toIEWIndex] = inst; @@ -929,6 +940,12 @@ DefaultRename<Impl>::doSquash(const InstSeqNum &squashed_seq_num, ThreadID tid) freeList->addReg(hb_it->newPhysReg); } + // Notify potential listeners that the register mapping needs to be + // removed because the instruction it was mapped to got squashed. Note + // that this is done before hb_it is incremented. + ppSquashInRename->notify(std::make_pair(hb_it->instSeqNum, + hb_it->newPhysReg)); + historyBuffer[tid].erase(hb_it++); ++renameUndoneMaps; |