12 files changed, 15 insertions, 15 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 7715ef57f..900a98aa0 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -96,7 +96,7 @@ class BaseDynInst : public FastAlloc, public RefCounted
 
     enum {
         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs,      /// Max dest regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs       /// Max dest regs
     };
 
     /** The StaticInst used by this BaseDynInst. */
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 0b21a1270..fdefcc980 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -171,4 +171,4 @@ Trace::ExeTracer *
 ExeTracerParams::create()
 {
     return new Trace::ExeTracer(this);
-};
+}
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 48620475a..4b48a157b 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -103,7 +103,7 @@ class InOrderDynInst : public FastAlloc, public RefCounted
 
     enum {
         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        /// Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs,      /// Max dest regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs       /// Max dest regs
     };
 
   public:
diff --git a/src/cpu/inorder/pipeline_traits.hh b/src/cpu/inorder/pipeline_traits.hh
index dd12a8f1d..5df61368f 100644
--- a/src/cpu/inorder/pipeline_traits.hh
+++ b/src/cpu/inorder/pipeline_traits.hh
@@ -77,7 +77,7 @@ namespace ThePipeline {
     //////////////////////////
     typedef ResourceSked ResSchedule;
     typedef ResourceSked* RSkedPtr;
-};
+}
 
 
 
diff --git a/src/cpu/inorder/resource.hh b/src/cpu/inorder/resource.hh
index 8822a3620..3c1a8cc47 100644
--- a/src/cpu/inorder/resource.hh
+++ b/src/cpu/inorder/resource.hh
@@ -263,7 +263,7 @@ class ResourceEvent : public Event
     /// (for InOrderCPU model).
     /// check src/sim/eventq.hh for more event priorities.
     enum InOrderPriority {
-        Resource_Event_Pri = 45,
+        Resource_Event_Pri = 45
     };
 
     /** The Resource Slot that this event is servicing */
diff --git a/src/cpu/inteltrace.cc b/src/cpu/inteltrace.cc
index 0d1d003d1..05bdc64d0 100644
--- a/src/cpu/inteltrace.cc
+++ b/src/cpu/inteltrace.cc
@@ -67,4 +67,4 @@ Trace::IntelTrace *
 IntelTraceParams::create()
 {
     return new Trace::IntelTrace(this);
-};
+}
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 1b101ede9..ed947d92f 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -81,7 +81,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
 
     enum {
         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
     };
 
   public:
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index ae76176ce..178a344f9 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -50,7 +50,7 @@
 class EndQuiesceEvent;
 namespace Kernel {
     class Statistics;
-};
+}
 
 /**
  * Derived ThreadContext class for use with the O3CPU.  It
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index ceab53c79..b1b8a66e4 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -73,8 +73,8 @@ class ProfileNode;
 namespace TheISA {
     namespace Kernel {
         class Statistics;
-    };
-};
+    }
+}
 
 /**
  * The SimpleThread object provides a combination of the ThreadState
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 7c5fcaa3a..db2cd817d 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -87,7 +87,7 @@ class StaticInst : public RefCounted
 
     enum {
         MaxInstSrcRegs = TheISA::MaxInstSrcRegs,        //< Max source regs
-        MaxInstDestRegs = TheISA::MaxInstDestRegs,      //< Max dest regs
+        MaxInstDestRegs = TheISA::MaxInstDestRegs       //< Max dest regs
     };
 
     /// Set of boolean static instruction properties.
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 119de1fe0..220c6cfc5 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -70,8 +70,8 @@ class System;
 namespace TheISA {
     namespace Kernel {
         class Statistics;
-    };
-};
+    }
+}
 
 /**
  * ThreadContext is the external interface to all thread state for
diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 153049812..3f58e4f14 100644
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -45,8 +45,8 @@ class ProfileNode;
 namespace TheISA {
     namespace Kernel {
         class Statistics;
-    };
-};
+    }
+}
 
 class Checkpoint;