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-rw-r--r--src/cpu/BaseCPU.py25
-rw-r--r--src/cpu/base.cc12
-rw-r--r--src/cpu/base.hh6
-rw-r--r--src/cpu/o3/cpu.cc4
-rw-r--r--src/cpu/ozone/cpu_impl.hh4
-rw-r--r--src/cpu/simple/base.cc4
6 files changed, 40 insertions, 15 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 1e3f0dbbc..c2385f6d0 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -39,14 +39,24 @@ default_tracer = ExeTracer()
if build_env['TARGET_ISA'] == 'alpha':
from AlphaTLB import AlphaDTB, AlphaITB
+ if build_env['FULL_SYSTEM']:
+ from AlphaInterrupts import AlphaInterrupts
elif build_env['TARGET_ISA'] == 'sparc':
from SparcTLB import SparcDTB, SparcITB
+ if build_env['FULL_SYSTEM']:
+ from SparcInterrupts import SparcInterrupts
elif build_env['TARGET_ISA'] == 'x86':
from X86TLB import X86DTB, X86ITB
+ if build_env['FULL_SYSTEM']:
+ from X86LocalApic import X86LocalApic
elif build_env['TARGET_ISA'] == 'mips':
from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
+ if build_env['FULL_SYSTEM']:
+ from MipsInterrupts import MipsInterrupts
elif build_env['TARGET_ISA'] == 'arm':
from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
+ if build_env['FULL_SYSTEM']:
+ from ArmInterrupts import ArmInterrupts
class BaseCPU(MemObject):
type = 'BaseCPU'
@@ -74,22 +84,37 @@ class BaseCPU(MemObject):
if build_env['TARGET_ISA'] == 'sparc':
dtb = Param.SparcDTB(SparcDTB(), "Data TLB")
itb = Param.SparcITB(SparcITB(), "Instruction TLB")
+ if build_env['FULL_SYSTEM']:
+ interrupts = Param.SparcInterrupts(
+ SparcInterrupts(), "Interrupt Controller")
elif build_env['TARGET_ISA'] == 'alpha':
dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
+ if build_env['FULL_SYSTEM']:
+ interrupts = Param.AlphaInterrupts(
+ AlphaInterrupts(), "Interrupt Controller")
elif build_env['TARGET_ISA'] == 'x86':
dtb = Param.X86DTB(X86DTB(), "Data TLB")
itb = Param.X86ITB(X86ITB(), "Instruction TLB")
+ if build_env['FULL_SYSTEM']:
+ interrupts = Param.X86LocalApic(
+ X86LocalApic(), "Interrupt Controller")
elif build_env['TARGET_ISA'] == 'mips':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
itb = Param.MipsITB(MipsITB(), "Instruction TLB")
tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
+ if build_env['FULL_SYSTEM']:
+ interrupts = Param.MipsInterrupts(
+ MipsInterrupts(), "Interrupt Controller")
elif build_env['TARGET_ISA'] == 'arm':
UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
dtb = Param.ArmDTB(ArmDTB(), "Data TLB")
itb = Param.ArmITB(ArmITB(), "Instruction TLB")
tlb = Param.ArmUTB(ArmUTB(), "Unified TLB")
+ if build_env['FULL_SYSTEM']:
+ interrupts = Param.ArmInterrupts(
+ ArmInterrupts(), "Interrupt Controller")
else:
print "Don't know what TLB to use for ISA %s" % \
build_env['TARGET_ISA']
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 1ca0dc14b..def1e9920 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -94,7 +94,7 @@ CPUProgressEvent::description() const
#if FULL_SYSTEM
BaseCPU::BaseCPU(Params *p)
- : MemObject(p), clock(p->clock), instCnt(0),
+ : MemObject(p), clock(p->clock), instCnt(0), interrupts(p->interrupts),
number_of_threads(p->numThreads), system(p->system),
phase(p->phase)
#else
@@ -381,33 +381,33 @@ BaseCPU::ProfileEvent::process()
void
BaseCPU::post_interrupt(int int_num, int index)
{
- interrupts.post(int_num, index);
+ interrupts->post(int_num, index);
}
void
BaseCPU::clear_interrupt(int int_num, int index)
{
- interrupts.clear(int_num, index);
+ interrupts->clear(int_num, index);
}
void
BaseCPU::clear_interrupts()
{
- interrupts.clear_all();
+ interrupts->clear_all();
}
void
BaseCPU::serialize(std::ostream &os)
{
SERIALIZE_SCALAR(instCnt);
- interrupts.serialize(os);
+ interrupts->serialize(os);
}
void
BaseCPU::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_SCALAR(instCnt);
- interrupts.unserialize(cp, section);
+ interrupts->unserialize(cp, section);
}
#endif // FULL_SYSTEM
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index c99efa834..a12c98ab0 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -107,13 +107,13 @@ class BaseCPU : public MemObject
protected:
// uint64_t interrupts[TheISA::NumInterruptLevels];
// uint64_t intstatus;
- TheISA::Interrupts interrupts;
+ TheISA::Interrupts * interrupts;
public:
TheISA::Interrupts *
getInterruptController()
{
- return &interrupts;
+ return interrupts;
}
virtual void post_interrupt(int int_num, int index);
@@ -121,7 +121,7 @@ class BaseCPU : public MemObject
virtual void clear_interrupts();
bool check_interrupts(ThreadContext * tc) const
- { return interrupts.check_interrupts(tc); }
+ { return interrupts->check_interrupts(tc); }
class ProfileEvent : public Event
{
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index ac816fc18..c110bbd50 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -906,7 +906,7 @@ Fault
FullO3CPU<Impl>::getInterrupts()
{
// Check if there are any outstanding interrupts
- return this->interrupts.getInterrupt(this->threadContexts[0]);
+ return this->interrupts->getInterrupt(this->threadContexts[0]);
}
template <class Impl>
@@ -920,7 +920,7 @@ FullO3CPU<Impl>::processInterrupts(Fault interrupt)
// @todo: Allow other threads to handle interrupts.
assert(interrupt != NoFault);
- this->interrupts.updateIntrInfo(this->threadContexts[0]);
+ this->interrupts->updateIntrInfo(this->threadContexts[0]);
DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
this->trap(interrupt, 0);
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 9c0b95a1a..94af07525 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -678,10 +678,10 @@ OzoneCPU<Impl>::processInterrupts()
// Check if there are any outstanding interrupts
//Handle the interrupts
- Fault interrupt = this->interrupts.getInterrupt(thread.getTC());
+ Fault interrupt = this->interrupts->getInterrupt(thread.getTC());
if (interrupt != NoFault) {
- this->interrupts.updateIntrInfo(thread.getTC());
+ this->interrupts->updateIntrInfo(thread.getTC());
interrupt->invoke(thread.getTC());
}
}
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 3fd699868..48e5db347 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -319,10 +319,10 @@ BaseSimpleCPU::checkForInterrupts()
{
#if FULL_SYSTEM
if (check_interrupts(tc)) {
- Fault interrupt = interrupts.getInterrupt(tc);
+ Fault interrupt = interrupts->getInterrupt(tc);
if (interrupt != NoFault) {
- interrupts.updateIntrInfo(tc);
+ interrupts->updateIntrInfo(tc);
interrupt->invoke(tc);
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 16:09:10 +0000