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-rw-r--r--src/cpu/o3/commit_impl.hh5
-rw-r--r--src/cpu/o3/decode_impl.hh5
-rw-r--r--src/cpu/o3/dyn_inst.hh1
-rw-r--r--src/cpu/o3/dyn_inst_impl.hh50
-rw-r--r--src/cpu/o3/fetch_impl.hh5
-rw-r--r--src/cpu/o3/iew_impl.hh5
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh8
-rw-r--r--src/cpu/o3/rename_impl.hh9
8 files changed, 61 insertions, 27 deletions
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 776968f8c..c7b255123 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -60,6 +60,7 @@
#include "debug/CommitRate.hh"
#include "debug/Drain.hh"
#include "debug/ExecFaulting.hh"
+#include "debug/O3PipeView.hh"
#include "params/DerivO3CPU.hh"
#include "sim/faults.hh"
#include "sim/full_system.hh"
@@ -1267,7 +1268,9 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
rob->retireHead(tid);
#if TRACING_ON
- head_inst->commitTick = curTick() - head_inst->fetchTick;
+ if (DTRACE(O3PipeView)) {
+ head_inst->commitTick = curTick() - head_inst->fetchTick;
+ }
#endif
// If this was a store, record it for this cycle.
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index f87ec0bfa..9ab672931 100644
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -47,6 +47,7 @@
#include "cpu/inst_seq.hh"
#include "debug/Activity.hh"
#include "debug/Decode.hh"
+#include "debug/O3PipeView.hh"
#include "params/DerivO3CPU.hh"
#include "sim/full_system.hh"
@@ -714,7 +715,9 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
--insts_available;
#if TRACING_ON
- inst->decodeTick = curTick() - inst->fetchTick;
+ if (DTRACE(O3PipeView)) {
+ inst->decodeTick = curTick() - inst->fetchTick;
+ }
#endif
// Ensure that if it was predicted as a branch, it really is a
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index de50bbda9..c8cdf7a1f 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -132,6 +132,7 @@ class BaseO3DynInst : public BaseDynInst<Impl>
int32_t issueTick;
int32_t completeTick;
int32_t commitTick;
+ int32_t storeTick;
#endif
/** Reads a misc. register, including any side-effects the read
diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index e37caf7f0..347d30324 100644
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -66,26 +66,35 @@ BaseO3DynInst<Impl>::BaseO3DynInst(StaticInstPtr _staticInst,
template <class Impl>BaseO3DynInst<Impl>::~BaseO3DynInst()
{
#if TRACING_ON
- Tick val, fetch = this->fetchTick;
- // Print info needed by the pipeline activity viewer.
- DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
- fetch,
- this->instAddr(),
- this->microPC(),
- this->seqNum,
- this->staticInst->disassemble(this->instAddr()));
- val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
- DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val);
- val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
- DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val);
- val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick;
- DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val);
- val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
- DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val);
- val = (this->completeTick == -1) ? 0 : fetch + this->completeTick;
- DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val);
- val = (this->commitTick == -1) ? 0 : fetch + this->commitTick;
- DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", val);
+ if (DTRACE(O3PipeView)) {
+ Tick fetch = this->fetchTick;
+ // fetchTick can be -1 if the instruction fetched outside the trace window.
+ if (fetch != -1) {
+ Tick val;
+ // Print info needed by the pipeline activity viewer.
+ DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
+ fetch,
+ this->instAddr(),
+ this->microPC(),
+ this->seqNum,
+ this->staticInst->disassemble(this->instAddr()));
+
+ val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
+ DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", val);
+ val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
+ DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", val);
+ val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick;
+ DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", val);
+ val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
+ DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", val);
+ val = (this->completeTick == -1) ? 0 : fetch + this->completeTick;
+ DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", val);
+ val = (this->commitTick == -1) ? 0 : fetch + this->commitTick;
+
+ Tick valS = (this->storeTick == -1) ? 0 : fetch + this->storeTick;
+ DPRINTFR(O3PipeView, "O3PipeView:retire:%llu:store:%llu\n", val, valS);
+ }
+ }
#endif
};
@@ -119,6 +128,7 @@ BaseO3DynInst<Impl>::initVars()
issueTick = -1;
completeTick = -1;
commitTick = -1;
+ storeTick = -1;
#endif
}
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 07033fc8a..e0eb10334 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -60,6 +60,7 @@
#include "debug/Activity.hh"
#include "debug/Drain.hh"
#include "debug/Fetch.hh"
+#include "debug/O3PipeView.hh"
#include "mem/packet.hh"
#include "params/DerivO3CPU.hh"
#include "sim/byteswap.hh"
@@ -1313,7 +1314,9 @@ DefaultFetch<Impl>::fetch(bool &status_change)
numInst++;
#if TRACING_ON
- instruction->fetchTick = curTick();
+ if (DTRACE(O3PipeView)) {
+ instruction->fetchTick = curTick();
+ }
#endif
nextPC = thisPC;
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 4b4f66a1f..5bd5f6ae9 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -56,6 +56,7 @@
#include "debug/Decode.hh"
#include "debug/Drain.hh"
#include "debug/IEW.hh"
+#include "debug/O3PipeView.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
@@ -1611,7 +1612,9 @@ DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
iewExecutedInsts++;
#if TRACING_ON
- inst->completeTick = curTick() - inst->fetchTick;
+ if (DTRACE(O3PipeView)) {
+ inst->completeTick = curTick() - inst->fetchTick;
+ }
#endif
//
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index a4cb56767..f0b27ba41 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -51,6 +51,7 @@
#include "debug/Activity.hh"
#include "debug/IEW.hh"
#include "debug/LSQUnit.hh"
+#include "debug/O3PipeView.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
@@ -1137,6 +1138,13 @@ LSQUnit<Impl>::completeStore(int store_idx)
"idx:%i\n",
storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
+#if TRACING_ON
+ if (DTRACE(O3PipeView)) {
+ storeQueue[store_idx].inst->storeTick =
+ curTick() - storeQueue[store_idx].inst->fetchTick;
+ }
+#endif
+
if (isStalled() &&
storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh
index 15a4ebc13..e27c66dcd 100644
--- a/src/cpu/o3/rename_impl.hh
+++ b/src/cpu/o3/rename_impl.hh
@@ -49,6 +49,7 @@
#include "cpu/o3/rename.hh"
#include "debug/Activity.hh"
#include "debug/Rename.hh"
+#include "debug/O3PipeView.hh"
#include "params/DerivO3CPU.hh"
using namespace std;
@@ -658,9 +659,6 @@ DefaultRename<Impl>::renameInsts(ThreadID tid)
++renamed_insts;
-#if TRACING_ON
- inst->renameTick = curTick() - inst->fetchTick;
-#endif
// Put instruction in rename queue.
toIEW->insts[toIEWIndex] = inst;
@@ -736,6 +734,11 @@ DefaultRename<Impl>::sortInsts()
for (int i = 0; i < insts_from_decode; ++i) {
DynInstPtr inst = fromDecode->insts[i];
insts[inst->threadNumber].push_back(inst);
+#if TRACING_ON
+ if (DTRACE(O3PipeView)) {
+ inst->renameTick = curTick() - inst->fetchTick;
+ }
+#endif
}
}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-12 06:20:19 +0000