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-rw-r--r--src/cpu/o3/commit.hh14
-rw-r--r--src/cpu/o3/cpu.cc17
-rw-r--r--src/cpu/o3/cpu.hh7
-rw-r--r--src/cpu/o3/fetch.hh10
-rw-r--r--src/cpu/o3/fetch_impl.hh24
-rw-r--r--src/cpu/simple/base.cc6
-rw-r--r--src/cpu/static_inst.hh15
7 files changed, 78 insertions, 15 deletions
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 1c0cd1037..860326283 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Korey Sewell
*/
#ifndef __CPU_O3_COMMIT_HH__
@@ -280,12 +281,20 @@ class DefaultCommit
/** Sets the PC of a specific thread. */
void setPC(uint64_t val, unsigned tid) { PC[tid] = val; }
- /** Reads the PC of a specific thread. */
+ /** Reads the next PC of a specific thread. */
uint64_t readNextPC(unsigned tid) { return nextPC[tid]; }
/** Sets the next PC of a specific thread. */
void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; }
+#if THE_ISA != ALPHA_ISA
+ /** Reads the next NPC of a specific thread. */
+ uint64_t readNextPC(unsigned tid) { return nextNPC[tid]; }
+
+ /** Sets the next NPC of a specific thread. */
+ void setNextPC(uint64_t val, unsigned tid) { nextNPC[tid] = val; }
+#endif
+
private:
/** Time buffer interface. */
TimeBuffer<TimeStruct> *timeBuffer;
@@ -397,6 +406,9 @@ class DefaultCommit
/** The next PC of each thread. */
Addr nextPC[Impl::MaxThreads];
+ /** The next NPC of each thread. */
+ Addr nextNPC[Impl::MaxThreads];
+
/** The sequence number of the youngest valid instruction in the ROB. */
InstSeqNum youngestSeqNum[Impl::MaxThreads];
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 430078860..a411fe42e 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Korey Sewell
*/
#include "config/full_system.hh"
@@ -925,6 +926,22 @@ FullO3CPU<Impl>::setNextPC(uint64_t val,unsigned tid)
commit.setNextPC(val, tid);
}
+#if THE_ISA != ALPHA_ISA
+template <class Impl>
+uint64_t
+FullO3CPU<Impl>::readNextNPC(unsigned tid)
+{
+ return commit.readNextNPC(tid);
+}
+
+template <class Impl>
+void
+FullO3CPU<Impl>::setNextNNPC(uint64_t val,unsigned tid)
+{
+ commit.setNextNPC(val, tid);
+}
+#endif
+
template <class Impl>
typename FullO3CPU<Impl>::ListIt
FullO3CPU<Impl>::addInst(DynInstPtr &inst)
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index bd6870114..b1ebcce9d 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Korey Sewell
*/
#ifndef __CPU_O3_CPU_HH__
@@ -299,6 +300,12 @@ class FullO3CPU : public BaseO3CPU
/** Sets the next PC of a specific thread. */
void setNextPC(uint64_t val, unsigned tid);
+ /** Reads the next NPC of a specific thread. */
+ uint64_t readNextNPC(unsigned tid);
+
+ /** Sets the next NPC of a specific thread. */
+ void setNextNPC(uint64_t val, unsigned tid);
+
/** Function to add instruction onto the head of the list of the
* instructions. Used when new instructions are fetched.
*/
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 476d4343f..790c28f09 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Korey Sewell
*/
#ifndef __CPU_O3_FETCH_HH__
@@ -335,6 +336,15 @@ class DefaultFetch
/** Per-thread next PC. */
Addr nextPC[Impl::MaxThreads];
+#if THE_ISA != ALPHA_ISA
+ /** Per-thread next Next PC.
+ * This is not a real register but is used for
+ * architectures that use a branch-delay slot.
+ * (such as MIPS or Sparc)
+ */
+ Addr nextNPC[Impl::MaxThreads];
+#endif
+
/** Memory request used to access cache. */
RequestPtr memReq[Impl::MaxThreads];
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index ab706ed47..7cbf0ab02 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Korey Sewell
*/
#include "config/use_checker.hh"
@@ -334,6 +335,9 @@ DefaultFetch<Impl>::initStage()
for (int tid = 0; tid < numThreads; tid++) {
PC[tid] = cpu->readPC(tid);
nextPC[tid] = cpu->readNextPC(tid);
+#if THE_ISA != ALPHA_ISA
+ nextNPC[tid] = cpu->readNextNPC(tid);
+#endif
}
}
@@ -408,6 +412,9 @@ DefaultFetch<Impl>::takeOverFrom()
stalls[i].commit = 0;
PC[i] = cpu->readPC(i);
nextPC[i] = cpu->readNextPC(i);
+#if THE_ISA != ALPHA_ISA
+ nextNPC[i] = cpu->readNextNPC(i);
+#endif
fetchStatus[i] = Running;
}
numInst = 0;
@@ -1028,7 +1035,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
fetch_PC = next_PC;
if (instruction->isQuiesce()) {
- warn("%lli: Quiesce instruction encountered, halting fetch!",
+ warn("cycle %lli: Quiesce instruction encountered, halting fetch!",
curTick);
fetchStatus[tid] = QuiescePending;
++numInst;
@@ -1049,8 +1056,17 @@ DefaultFetch<Impl>::fetch(bool &status_change)
if (fault == NoFault) {
DPRINTF(Fetch, "[tid:%i]: Setting PC to %08p.\n",tid, next_PC);
+#if THE_ISA == ALPHA_ISA
+ PC[tid] = next_PC;
+ nextPC[tid] = next_PC + instSize;
+#else
PC[tid] = next_PC;
nextPC[tid] = next_PC + instSize;
+ nextPC[tid] = next_PC + instSize;
+
+ thread->setNextPC(thread->readNextNPC());
+ thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
+#endif
} else {
// We shouldn't be in an icache miss and also have a fault (an ITB
// miss)
@@ -1093,9 +1109,9 @@ DefaultFetch<Impl>::fetch(bool &status_change)
fetchStatus[tid] = TrapPending;
status_change = true;
- warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
+ warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
#else // !FULL_SYSTEM
- warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
+ warn("cycle %lli: fault (%d) detected @ PC %08p", curTick, fault, PC[tid]);
#endif // FULL_SYSTEM
}
}
@@ -1264,6 +1280,6 @@ int
DefaultFetch<Impl>::branchCount()
{
list<unsigned>::iterator threads = (*activeThreads).begin();
-
+ warn("Branch Count Fetch policy unimplemented\n");
return *threads;
}
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index d94b0e079..b4258fce6 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
+ * Korey Sewell
*/
#include "arch/utility.hh"
@@ -358,8 +359,13 @@ Fault
BaseSimpleCPU::setupFetchRequest(Request *req)
{
// set up memory request for instruction fetch
+#if THE_ISA == ALPHA_ISA
+ DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
+ thread->readNextPC());
+#else
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
thread->readNextPC(),thread->readNextNPC());
+#endif
req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst),
(FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0,
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index bea52f510..a98078634 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -34,6 +34,7 @@
#include <bitset>
#include <string>
+#include "base/bitfield.hh"
#include "base/hashmap.hh"
#include "base/misc.hh"
#include "base/refcnt.hh"
@@ -411,16 +412,10 @@ class StaticInst : public StaticInstBase
//This is defined as inline below.
static StaticInstPtr decode(ExtMachInst mach_inst);
- //MIPS Decoder Debug Functions
- int getOpcode() { return (machInst & 0xFC000000) >> 26 ; }//31..26
- int getRs() { return (machInst & 0x03E00000) >> 21; } //25...21
- int getRt() { return (machInst & 0x001F0000) >> 16; } //20...16
- int getRd() { return (machInst & 0x0000F800) >> 11; } //15...11
- int getImm() { return (machInst & 0x0000FFFF); } //15...0
- int getFunction(){ return (machInst & 0x0000003F); }//5...0
- int getBranch(){ return (machInst & 0x0000FFFF); }//15...0
- int getJump(){ return (machInst & 0x03FFFFFF); }//5...0
- int getHint(){ return (machInst & 0x000007C0) >> 6; } //10...6
+ /// Return opcode of machine instruction
+ uint32_t getOpcode() { return bits(machInst, 31, 26);}
+
+ /// Return name of machine instruction
std::string getName() { return mnemonic; }
};
generated by cgit v1.2.3 (git 2.25.1) at 2025-01-22 15:36:48 +0000