5 files changed, 18 insertions, 27 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index a0d26a8ab..c2e6f6185 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -250,10 +250,9 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
 
     // Now do the access.
     if (fault == NoFault) {
-        data_read_pkt->reset();
         data_read_pkt->reinitFromRequest();
 
-        dcache_complete = dcachePort.sendAtomic(data_read_pkt);
+        dcache_latency = dcachePort.sendAtomic(data_read_pkt);
         dcache_access = true;
 
         assert(data_read_pkt->result == Packet::Success);
@@ -329,12 +328,11 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 
     // Now do the access.
     if (fault == NoFault) {
-        data_write_pkt->reset();
         data = htog(data);
-        data_write_pkt->dataStatic(&data);
         data_write_pkt->reinitFromRequest();
+        data_write_pkt->dataStatic(&data);
 
-        dcache_complete = dcachePort.sendAtomic(data_write_pkt);
+        dcache_latency = dcachePort.sendAtomic(data_write_pkt);
         dcache_access = true;
 
         assert(data_write_pkt->result == Packet::Success);
@@ -411,11 +409,12 @@ AtomicSimpleCPU::tick()
         checkForInterrupts();
 
         ifetch_req->resetMin();
-        ifetch_pkt->reset();
-        Fault fault = setupFetchPacket(ifetch_pkt);
+        Fault fault = setupFetchRequest(ifetch_req);
 
         if (fault == NoFault) {
-            Tick icache_complete = icachePort.sendAtomic(ifetch_pkt);
+            ifetch_pkt->reinitFromRequest();
+
+            Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
             // ifetch_req is initialized to read the instruction directly
             // into the CPU object's inst field.
 
@@ -430,9 +429,9 @@ AtomicSimpleCPU::tick()
                 // cycle time.  If not, the next tick event may get
                 // scheduled at a non-integer multiple of the CPU
                 // cycle time.
-                Tick icache_stall = icache_complete - curTick - cycles(1);
+                Tick icache_stall = icache_latency - cycles(1);
                 Tick dcache_stall =
-                    dcache_access ? dcache_complete - curTick - cycles(1) : 0;
+                    dcache_access ? dcache_latency - cycles(1) : 0;
                 latency += icache_stall + dcache_stall;
             }
 
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 65269bd6d..8c76fbdc8 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -116,7 +116,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     Packet  *data_write_pkt;
 
     bool dcache_access;
-    Tick dcache_complete;
+    Tick dcache_latency;
 
   public:
 
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 18f170449..2e9b4b81f 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -351,29 +351,21 @@ BaseSimpleCPU::checkForInterrupts()
 
 
 Fault
-BaseSimpleCPU::setupFetchPacket(Packet *ifetch_pkt)
+BaseSimpleCPU::setupFetchRequest(Request *req)
 {
-    // Try to fetch an instruction
-
     // set up memory request for instruction fetch
-
     DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(),
             cpuXC->readNextPC(),cpuXC->readNextNPC());
 
-    Request *ifetch_req = ifetch_pkt->req;
-    ifetch_req->setVaddr(cpuXC->readPC() & ~3);
-    ifetch_req->setTime(curTick);
+    req->setVaddr(cpuXC->readPC() & ~3);
+    req->setTime(curTick);
 #if FULL_SYSTEM
-    ifetch_req->setFlags((cpuXC->readPC() & 1) ? PHYSICAL : 0);
+    req->setFlags((cpuXC->readPC() & 1) ? PHYSICAL : 0);
 #else
-    ifetch_req->setFlags(0);
+    req->setFlags(0);
 #endif
 
-    Fault fault = cpuXC->translateInstReq(ifetch_req);
-
-    if (fault == NoFault) {
-        ifetch_pkt->reinitFromRequest();
-    }
+    Fault fault = cpuXC->translateInstReq(req);
 
     return fault;
 }
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 4c0e6f3c7..dbeb6afce 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -129,7 +129,7 @@ class BaseSimpleCPU : public BaseCPU
     StaticInstPtr curStaticInst;
 
     void checkForInterrupts();
-    Fault setupFetchPacket(Packet *ifetch_pkt);
+    Fault setupFetchRequest(Request *req);
     void preExecute();
     void postExecute();
     void advancePC(Fault fault);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 5f094d033..ed0c2da94 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -342,11 +342,11 @@ TimingSimpleCPU::fetch()
 
     Request *ifetch_req = new Request(true);
     ifetch_req->setSize(sizeof(MachInst));
+    Fault fault = setupFetchRequest(ifetch_req);
 
     ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
     ifetch_pkt->dataStatic(&inst);
 
-    Fault fault = setupFetchPacket(ifetch_pkt);
     if (fault == NoFault) {
         if (!icachePort.sendTiming(ifetch_pkt)) {
             // Need to wait for retry