diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/BaseCPU.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 51d447f0b..ef9b54f3f 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -97,7 +97,7 @@ class BaseCPU(MemObject): dtb = Param.X86DTB(X86DTB(), "Data TLB") itb = Param.X86ITB(X86ITB(), "Instruction TLB") if build_env['FULL_SYSTEM']: - _localApic = X86LocalApic(pio_addr=0xa000000000000000) + _localApic = X86LocalApic(pio_addr=0x2000000000000000) interrupts = \ Param.X86LocalApic(_localApic, "Interrupt Controller") elif build_env['TARGET_ISA'] == 'mips': |