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-rw-r--r--src/cpu/simple/atomic.cc50
-rw-r--r--src/cpu/simple/atomic.hh4
-rw-r--r--src/cpu/simple/base.cc22
-rw-r--r--src/cpu/simple/base.hh2
-rw-r--r--src/cpu/simple/timing.cc40
-rw-r--r--src/cpu/simple/timing.hh4
6 files changed, 45 insertions, 77 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 3cad6e43f..99b022c07 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -106,11 +106,10 @@ AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
}
-Packet *
+void
AtomicSimpleCPU::CpuPort::recvRetry()
{
panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
- return NULL;
}
@@ -121,26 +120,17 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
{
_status = Idle;
- ifetch_req = new Request(true);
- ifetch_req->setAsid(0);
- // @todo fix me and get the real cpu iD!!!
- ifetch_req->setCpuNum(0);
- ifetch_req->setSize(sizeof(MachInst));
+ // @todo fix me and get the real cpu id & thread number!!!
+ ifetch_req = new Request();
ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
ifetch_pkt->dataStatic(&inst);
- data_read_req = new Request(true);
- // @todo fix me and get the real cpu iD!!!
- data_read_req->setCpuNum(0);
- data_read_req->setAsid(0);
+ data_read_req = new Request();
data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
Packet::Broadcast);
data_read_pkt->dataStatic(&dataReg);
- data_write_req = new Request(true);
- // @todo fix me and get the real cpu iD!!!
- data_write_req->setCpuNum(0);
- data_write_req->setAsid(0);
+ data_write_req = new Request();
data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
Packet::Broadcast);
}
@@ -237,10 +227,7 @@ template <class T>
Fault
AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
{
- data_read_req->setVaddr(addr);
- data_read_req->setSize(sizeof(T));
- data_read_req->setFlags(flags);
- data_read_req->setTime(curTick);
+ data_read_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
if (traceData) {
traceData->setAddr(addr);
@@ -251,10 +238,9 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
// Now do the access.
if (fault == NoFault) {
- data_read_pkt->reset();
data_read_pkt->reinitFromRequest();
- dcache_complete = dcachePort.sendAtomic(data_read_pkt);
+ dcache_latency = dcachePort.sendAtomic(data_read_pkt);
dcache_access = true;
assert(data_read_pkt->result == Packet::Success);
@@ -316,10 +302,7 @@ template <class T>
Fault
AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
- data_write_req->setVaddr(addr);
- data_write_req->setTime(curTick);
- data_write_req->setSize(sizeof(T));
- data_write_req->setFlags(flags);
+ data_write_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
if (traceData) {
traceData->setAddr(addr);
@@ -330,12 +313,11 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
// Now do the access.
if (fault == NoFault) {
- data_write_pkt->reset();
data = htog(data);
- data_write_pkt->dataStatic(&data);
data_write_pkt->reinitFromRequest();
+ data_write_pkt->dataStatic(&data);
- dcache_complete = dcachePort.sendAtomic(data_write_pkt);
+ dcache_latency = dcachePort.sendAtomic(data_write_pkt);
dcache_access = true;
assert(data_write_pkt->result == Packet::Success);
@@ -411,12 +393,12 @@ AtomicSimpleCPU::tick()
checkForInterrupts();
- ifetch_req->resetMin();
- ifetch_pkt->reset();
- Fault fault = setupFetchPacket(ifetch_pkt);
+ Fault fault = setupFetchRequest(ifetch_req);
if (fault == NoFault) {
- Tick icache_complete = icachePort.sendAtomic(ifetch_pkt);
+ ifetch_pkt->reinitFromRequest();
+
+ Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
// ifetch_req is initialized to read the instruction directly
// into the CPU object's inst field.
@@ -431,9 +413,9 @@ AtomicSimpleCPU::tick()
// cycle time. If not, the next tick event may get
// scheduled at a non-integer multiple of the CPU
// cycle time.
- Tick icache_stall = icache_complete - curTick - cycles(1);
+ Tick icache_stall = icache_latency - cycles(1);
Tick dcache_stall =
- dcache_access ? dcache_complete - curTick - cycles(1) : 0;
+ dcache_access ? dcache_latency - cycles(1) : 0;
latency += icache_stall + dcache_stall;
}
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index ab3a3e8ef..8c76fbdc8 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -98,7 +98,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
virtual void recvStatusChange(Status status);
- virtual Packet *recvRetry();
+ virtual void recvRetry();
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
@@ -116,7 +116,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
Packet *data_write_pkt;
bool dcache_access;
- Tick dcache_complete;
+ Tick dcache_latency;
public:
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 18f170449..2e979870c 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -351,29 +351,17 @@ BaseSimpleCPU::checkForInterrupts()
Fault
-BaseSimpleCPU::setupFetchPacket(Packet *ifetch_pkt)
+BaseSimpleCPU::setupFetchRequest(Request *req)
{
- // Try to fetch an instruction
-
// set up memory request for instruction fetch
-
DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(),
cpuXC->readNextPC(),cpuXC->readNextNPC());
- Request *ifetch_req = ifetch_pkt->req;
- ifetch_req->setVaddr(cpuXC->readPC() & ~3);
- ifetch_req->setTime(curTick);
-#if FULL_SYSTEM
- ifetch_req->setFlags((cpuXC->readPC() & 1) ? PHYSICAL : 0);
-#else
- ifetch_req->setFlags(0);
-#endif
-
- Fault fault = cpuXC->translateInstReq(ifetch_req);
+ req->setVirt(0, cpuXC->readPC() & ~3, sizeof(MachInst),
+ (FULL_SYSTEM && (cpuXC->readPC() & 1)) ? PHYSICAL : 0,
+ cpuXC->readPC());
- if (fault == NoFault) {
- ifetch_pkt->reinitFromRequest();
- }
+ Fault fault = cpuXC->translateInstReq(req);
return fault;
}
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 4c0e6f3c7..dbeb6afce 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -129,7 +129,7 @@ class BaseSimpleCPU : public BaseCPU
StaticInstPtr curStaticInst;
void checkForInterrupts();
- Fault setupFetchPacket(Packet *ifetch_pkt);
+ Fault setupFetchRequest(Request *req);
void preExecute();
void postExecute();
void advancePC(Fault fault);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 7cdcdafa1..9cccb97f7 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -172,12 +172,10 @@ template <class T>
Fault
TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
{
- Request *data_read_req = new Request(true);
+ // need to fill in CPU & thread IDs here
+ Request *data_read_req = new Request();
- data_read_req->setVaddr(addr);
- data_read_req->setSize(sizeof(T));
- data_read_req->setFlags(flags);
- data_read_req->setTime(curTick);
+ data_read_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
if (traceData) {
traceData->setAddr(data_read_req->getVaddr());
@@ -255,11 +253,9 @@ template <class T>
Fault
TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
- Request *data_write_req = new Request(true);
- data_write_req->setVaddr(addr);
- data_write_req->setTime(curTick);
- data_write_req->setSize(sizeof(T));
- data_write_req->setFlags(flags);
+ // need to fill in CPU & thread IDs here
+ Request *data_write_req = new Request();
+ data_write_req->setVirt(0, addr, sizeof(T), flags, cpuXC->readPC());
// translate to physical address
Fault fault = cpuXC->translateDataWriteReq(data_write_req);
@@ -340,13 +336,13 @@ TimingSimpleCPU::fetch()
{
checkForInterrupts();
- Request *ifetch_req = new Request(true);
- ifetch_req->setSize(sizeof(MachInst));
+ // need to fill in CPU & thread IDs here
+ Request *ifetch_req = new Request();
+ Fault fault = setupFetchRequest(ifetch_req);
ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
ifetch_pkt->dataStatic(&inst);
- Fault fault = setupFetchPacket(ifetch_pkt);
if (fault == NoFault) {
if (!icachePort.sendTiming(ifetch_pkt)) {
// Need to wait for retry
@@ -419,17 +415,18 @@ TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
return true;
}
-Packet *
+void
TimingSimpleCPU::IcachePort::recvRetry()
{
// we shouldn't get a retry unless we have a packet that we're
// waiting to transmit
assert(cpu->ifetch_pkt != NULL);
assert(cpu->_status == IcacheRetry);
- cpu->_status = IcacheWaitResponse;
Packet *tmp = cpu->ifetch_pkt;
- cpu->ifetch_pkt = NULL;
- return tmp;
+ if (sendTiming(tmp)) {
+ cpu->_status = IcacheWaitResponse;
+ cpu->ifetch_pkt = NULL;
+ }
}
void
@@ -459,17 +456,18 @@ TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
return true;
}
-Packet *
+void
TimingSimpleCPU::DcachePort::recvRetry()
{
// we shouldn't get a retry unless we have a packet that we're
// waiting to transmit
assert(cpu->dcache_pkt != NULL);
assert(cpu->_status == DcacheRetry);
- cpu->_status = DcacheWaitResponse;
Packet *tmp = cpu->dcache_pkt;
- cpu->dcache_pkt = NULL;
- return tmp;
+ if (sendTiming(tmp)) {
+ cpu->_status = DcacheWaitResponse;
+ cpu->dcache_pkt = NULL;
+ }
}
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index b46631d5a..cb37824bc 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -100,7 +100,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
virtual bool recvTiming(Packet *pkt);
- virtual Packet *recvRetry();
+ virtual void recvRetry();
};
class DcachePort : public CpuPort
@@ -115,7 +115,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
virtual bool recvTiming(Packet *pkt);
- virtual Packet *recvRetry();
+ virtual void recvRetry();
};
IcachePort icachePort;
generated by cgit v1.2.3 (git 2.25.1) at 2024-09-04 16:29:04 +0000