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-rw-r--r--src/cpu/FuncUnit.py4
-rw-r--r--src/cpu/op_class.hh8
2 files changed, 10 insertions, 2 deletions
diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py
index d5983055d..e985a648a 100644
--- a/src/cpu/FuncUnit.py
+++ b/src/cpu/FuncUnit.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2010 ARM Limited
+# Copyright (c) 2010,2018 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -50,6 +50,8 @@ class OpClass(Enum):
'SimdSqrt', 'SimdFloatAdd', 'SimdFloatAlu', 'SimdFloatCmp',
'SimdFloatCvt', 'SimdFloatDiv', 'SimdFloatMisc', 'SimdFloatMult',
'SimdFloatMultAcc', 'SimdFloatSqrt',
+ 'SimdSha1Hash', 'SimdSha1Hash2', 'SimdSha256Hash',
+ 'SimdSha256Hash2', 'SimdShaSigma2', 'SimdShaSigma3',
'MemRead', 'MemWrite', 'FloatMemRead', 'FloatMemWrite',
'IprAccess', 'InstPrefetch']
diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh
index adc7bae97..a4cadb96e 100644
--- a/src/cpu/op_class.hh
+++ b/src/cpu/op_class.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2010,2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -83,6 +83,12 @@ static const OpClass SimdFloatMiscOp = Enums::SimdFloatMisc;
static const OpClass SimdFloatMultOp = Enums::SimdFloatMult;
static const OpClass SimdFloatMultAccOp = Enums::SimdFloatMultAcc;
static const OpClass SimdFloatSqrtOp = Enums::SimdFloatSqrt;
+static const OpClass SimdSha1HashOp = Enums::SimdSha1Hash;
+static const OpClass SimdSha1Hash2Op = Enums::SimdSha1Hash2;
+static const OpClass SimdSha256HashOp = Enums::SimdSha256Hash;
+static const OpClass SimdSha256Hash2Op = Enums::SimdSha256Hash2;
+static const OpClass SimdShaSigma2Op = Enums::SimdShaSigma2;
+static const OpClass SimdShaSigma3Op = Enums::SimdShaSigma3;
static const OpClass MemReadOp = Enums::MemRead;
static const OpClass MemWriteOp = Enums::MemWrite;
static const OpClass FloatMemReadOp = Enums::FloatMemRead;