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-rw-r--r--src/cpu/BaseCPU.py19
-rw-r--r--src/cpu/base.cc6
-rw-r--r--src/cpu/o3/O3CPU.py4
-rw-r--r--src/cpu/o3/cpu.cc13
-rw-r--r--src/cpu/o3/cpu.hh3
5 files changed, 31 insertions, 14 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index b5c203742..50a8501e2 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -167,15 +167,16 @@ class BaseCPU(MemObject):
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
- if buildEnv['TARGET_ISA'] == 'x86' and iwc and dwc:
- self.itb_walker_cache = iwc
- self.dtb_walker_cache = dwc
- self.itb.walker.port = iwc.cpu_side
- self.dtb.walker.port = dwc.cpu_side
- self._cached_ports += ["itb_walker_cache.mem_side", \
- "dtb_walker_cache.mem_side"]
- elif buildEnv['TARGET_ISA'] == 'arm':
- self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
+ if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
+ if iwc and dwc:
+ self.itb_walker_cache = iwc
+ self.dtb_walker_cache = dwc
+ self.itb.walker.port = iwc.cpu_side
+ self.dtb.walker.port = dwc.cpu_side
+ self._cached_ports += ["itb_walker_cache.mem_side", \
+ "dtb_walker_cache.mem_side"]
+ else:
+ self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 6e2de0baf..a0785ac10 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -184,7 +184,11 @@ BaseCPU::BaseCPU(Params *p)
functionTracingEnabled = false;
if (p->function_trace) {
- functionTraceStream = simout.find(csprintf("ftrace.%s", name()));
+ const string fname = csprintf("ftrace.%s", name());
+ functionTraceStream = simout.find(fname);
+ if (!functionTraceStream)
+ functionTraceStream = simout.create(fname);
+
currentFunctionStart = currentFunctionEnd = 0;
functionEntryTick = p->function_trace_start;
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 51643c169..1d8950a73 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -142,7 +142,3 @@ class DerivO3CPU(BaseCPU):
smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
- def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
- BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
- self.icache.tgts_per_mshr = 20
- self.dcache.tgts_per_mshr = 20
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index bb5ccc17e..5d3af6c70 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -438,6 +438,12 @@ FullO3CPU<Impl>::regStats()
"to idling")
.prereq(idleCycles);
+ quiesceCycles
+ .name(name() + ".quiesceCycles")
+ .desc("Total number of cycles that CPU has spent quiesced or waiting "
+ "for an interrupt")
+ .prereq(quiesceCycles);
+
// Number of Instructions simulated
// --------------------------------
// Should probably be in Base CPU but need templated
@@ -682,6 +688,8 @@ FullO3CPU<Impl>::activateContext(ThreadID tid, int delay)
activityRec.activity();
fetch.wakeFromQuiesce();
+ quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
+
lastActivatedCycle = curTick();
_status = Running;
@@ -716,6 +724,9 @@ FullO3CPU<Impl>::suspendContext(ThreadID tid)
if ((activeThreads.size() == 1 && !deallocated) ||
activeThreads.size() == 0)
unscheduleTickEvent();
+
+ DPRINTF(Quiesce, "Suspending Context\n");
+ lastRunningCycle = curTick();
_status = Idle;
}
@@ -1193,6 +1204,8 @@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
}
if (!tickEvent.scheduled())
schedule(tickEvent, nextCycle());
+
+ lastRunningCycle = curTick();
}
template <class Impl>
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index b5654dee1..7580106ad 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -713,6 +713,9 @@ class FullO3CPU : public BaseO3CPU
Stats::Scalar timesIdled;
/** Stat for total number of cycles the CPU spends descheduled. */
Stats::Scalar idleCycles;
+ /** Stat for total number of cycles the CPU spends descheduled due to a
+ * quiesce operation or waiting for an interrupt. */
+ Stats::Scalar quiesceCycles;
/** Stat for the number of committed instructions per thread. */
Stats::Vector committedInsts;
/** Stat for the total number of committed instructions. */