5 files changed, 3 insertions, 56 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 9ed2cb789..8c658b196 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -145,9 +145,6 @@ class BaseCPU(MemObject):
     defer_registration = Param.Bool(False,
         "defer registration with system (for sampling)")
 
-    clock = Param.Clock('1t', "clock speed")
-    phase = Param.Latency('0ns', "clock phase")
-
     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 
     icache_port = MasterPort("Instruction Port")
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 893b0e06b..c1b1e6d36 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -115,15 +115,12 @@ CPUProgressEvent::description() const
 }
 
 BaseCPU::BaseCPU(Params *p, bool is_checker)
-    : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
+    : MemObject(p), instCnt(0), _cpuId(p->cpu_id),
       _instMasterId(p->system->getMasterId(name() + ".inst")),
       _dataMasterId(p->system->getMasterId(name() + ".data")),
       interrupts(p->interrupts),
-      numThreads(p->numThreads), system(p->system),
-      phase(p->phase)
+      numThreads(p->numThreads), system(p->system)
 {
-//    currentTick = curTick();
-
     // if Python did not provide a valid ID, do it here
     if (_cpuId == -1 ) {
         _cpuId = cpuList.size();
@@ -317,27 +314,6 @@ BaseCPU::getMasterPort(const string &if_name, int idx)
         return MemObject::getMasterPort(if_name, idx);
 }
 
-Tick
-BaseCPU::nextCycle()
-{
-    Tick next_tick = curTick() - phase + clock - 1;
-    next_tick -= (next_tick % clock);
-    next_tick += phase;
-    return next_tick;
-}
-
-Tick
-BaseCPU::nextCycle(Tick begin_tick)
-{
-    Tick next_tick = begin_tick;
-    if (next_tick % clock != 0)
-        next_tick = next_tick - (next_tick % clock) + clock;
-    next_tick += phase;
-
-    assert(next_tick >= curTick());
-    return next_tick;
-}
-
 void
 BaseCPU::registerThreadContexts()
 {
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index b99b25d17..aab6ac4ca 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -88,8 +88,7 @@ class CPUProgressEvent : public Event
 class BaseCPU : public MemObject
 {
   protected:
-    // CPU's clock period in terms of the number of ticks of curTime.
-    Tick clock;
+
     // @todo remove me after debugging with legion done
     Tick instCnt;
     // every cpu has an id, put it in the base cpu
@@ -174,30 +173,11 @@ class BaseCPU : public MemObject
      */
     MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
 
-//    Tick currentTick;
-    inline Tick frequency() const { return SimClock::Frequency / clock; }
-    inline Tick ticks(int numCycles) const { return clock * numCycles; }
-    inline Tick curCycle() const { return curTick() / clock; }
-    inline Tick tickToCycles(Tick val) const { return val / clock; }
     inline void workItemBegin() { numWorkItemsStarted++; }
     inline void workItemEnd() { numWorkItemsCompleted++; }
     // @todo remove me after debugging with legion done
     Tick instCount() { return instCnt; }
 
-    /** The next cycle the CPU should be scheduled, given a cache
-     * access or quiesce event returning on this cycle.  This function
-     * may return curTick() if the CPU should run on the current cycle.
-     */
-    Tick nextCycle();
-
-    /** The next cycle the CPU should be scheduled, given a cache
-     * access or quiesce event returning on the given Tick.  This
-     * function may return curTick() if the CPU should run on the
-     * current cycle.
-     * @param begin_tick The tick that the event is completing on.
-     */
-    Tick nextCycle(Tick begin_tick);
-
     TheISA::MicrocodeRom microcodeRom;
 
   protected:
@@ -328,8 +308,6 @@ class BaseCPU : public MemObject
 
     System *system;
 
-    Tick phase;
-
     /**
      * Serialize this object to the given output stream.
      * @param os The stream to serialize to.
diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh
index 52e32d72d..94617c876 100644
--- a/src/cpu/testers/memtest/memtest.hh
+++ b/src/cpu/testers/memtest/memtest.hh
@@ -56,8 +56,6 @@ class MemTest : public MemObject
     // register statistics
     virtual void regStats();
 
-    inline Tick ticks(int numCycles) const { return numCycles; }
-
     // main simulation loop (one cycle)
     void tick();
 
diff --git a/src/cpu/testers/networktest/networktest.hh b/src/cpu/testers/networktest/networktest.hh
index aec74a484..76119e678 100644
--- a/src/cpu/testers/networktest/networktest.hh
+++ b/src/cpu/testers/networktest/networktest.hh
@@ -51,8 +51,6 @@ class NetworkTest : public MemObject
 
     virtual void init();
 
-    inline Tick ticks(int numCycles) const { return numCycles; }
-
     // main simulation loop (one cycle)
     void tick();