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-rw-r--r--src/cpu/BaseCPU.py6
-rw-r--r--src/cpu/CheckerCPU.py1
-rw-r--r--src/cpu/ExeTracer.py1
-rw-r--r--src/cpu/FuncUnit.py2
-rw-r--r--src/cpu/IntelTrace.py1
-rw-r--r--src/cpu/IntrControl.py1
-rw-r--r--src/cpu/LegionTrace.py1
-rw-r--r--src/cpu/NativeTrace.py1
-rw-r--r--src/cpu/inorder/InOrderCPU.py1
-rw-r--r--src/cpu/inorder/InOrderTrace.py1
-rw-r--r--src/cpu/inteltrace.hh3
-rw-r--r--src/cpu/o3/FUPool.py1
-rw-r--r--src/cpu/simple/AtomicSimpleCPU.py1
-rw-r--r--src/cpu/simple/BaseSimpleCPU.py1
-rw-r--r--src/cpu/simple/TimingSimpleCPU.py1
-rw-r--r--src/cpu/static_inst.hh2
-rw-r--r--src/cpu/testers/directedtest/RubyDirectedTester.py4
-rw-r--r--src/cpu/testers/memtest/MemTest.py1
-rw-r--r--src/cpu/testers/networktest/NetworkTest.py1
-rw-r--r--src/cpu/testers/rubytest/RubyTester.py1
-rw-r--r--src/cpu/testers/traffic_gen/TrafficGen.py1
21 files changed, 25 insertions, 8 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 331957749..dfbd459fd 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -76,11 +76,7 @@ elif buildEnv['TARGET_ISA'] == 'power':
class BaseCPU(MemObject):
type = 'BaseCPU'
abstract = True
-
- @classmethod
- def export_method_cxx_predecls(cls, code):
- code('#include "cpu/base.hh"')
-
+ cxx_header = "cpu/base.hh"
@classmethod
def export_methods(cls, code):
diff --git a/src/cpu/CheckerCPU.py b/src/cpu/CheckerCPU.py
index a6b5da5d7..f08b59f20 100644
--- a/src/cpu/CheckerCPU.py
+++ b/src/cpu/CheckerCPU.py
@@ -32,6 +32,7 @@ from BaseCPU import BaseCPU
class CheckerCPU(BaseCPU):
type = 'CheckerCPU'
abstract = True
+ cxx_header = "cpu/checker/cpu.hh"
exitOnError = Param.Bool(False, "Exit on an error")
updateOnError = Param.Bool(False,
"Update the checker with the main CPU's state on an error")
diff --git a/src/cpu/ExeTracer.py b/src/cpu/ExeTracer.py
index 5754f5d5b..f672fd65f 100644
--- a/src/cpu/ExeTracer.py
+++ b/src/cpu/ExeTracer.py
@@ -33,3 +33,4 @@ from InstTracer import InstTracer
class ExeTracer(InstTracer):
type = 'ExeTracer'
cxx_class = 'Trace::ExeTracer'
+ cxx_header = "cpu/exetrace.hh"
diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py
index 92d7e13ca..0bb23e876 100644
--- a/src/cpu/FuncUnit.py
+++ b/src/cpu/FuncUnit.py
@@ -53,11 +53,13 @@ class OpClass(Enum):
class OpDesc(SimObject):
type = 'OpDesc'
+ cxx_header = "cpu/func_unit.hh"
issueLat = Param.Cycles(1, "cycles until another can be issued")
opClass = Param.OpClass("type of operation")
opLat = Param.Cycles(1, "cycles until result is available")
class FUDesc(SimObject):
type = 'FUDesc'
+ cxx_header = "cpu/func_unit.hh"
count = Param.Int("number of these FU's available")
opList = VectorParam.OpDesc("operation classes for this FU type")
diff --git a/src/cpu/IntelTrace.py b/src/cpu/IntelTrace.py
index 3642f3174..6319ed1aa 100644
--- a/src/cpu/IntelTrace.py
+++ b/src/cpu/IntelTrace.py
@@ -33,3 +33,4 @@ from InstTracer import InstTracer
class IntelTrace(InstTracer):
type = 'IntelTrace'
cxx_class = 'Trace::IntelTrace'
+ cxx_header = "cpu/inteltrace.hh"
diff --git a/src/cpu/IntrControl.py b/src/cpu/IntrControl.py
index eb4b1696b..72ea6ccb9 100644
--- a/src/cpu/IntrControl.py
+++ b/src/cpu/IntrControl.py
@@ -31,4 +31,5 @@ from m5.params import *
from m5.proxy import *
class IntrControl(SimObject):
type = 'IntrControl'
+ cxx_header = "cpu/intr_control.hh"
sys = Param.System(Parent.any, "the system we are part of")
diff --git a/src/cpu/LegionTrace.py b/src/cpu/LegionTrace.py
index d450dd00e..8b2a7cd85 100644
--- a/src/cpu/LegionTrace.py
+++ b/src/cpu/LegionTrace.py
@@ -33,3 +33,4 @@ from InstTracer import InstTracer
class LegionTrace(InstTracer):
type = 'LegionTrace'
cxx_class = 'Trace::LegionTrace'
+ cxx_header = "cpu/legiontrace.hh"
diff --git a/src/cpu/NativeTrace.py b/src/cpu/NativeTrace.py
index dba6de067..fbcb341f0 100644
--- a/src/cpu/NativeTrace.py
+++ b/src/cpu/NativeTrace.py
@@ -34,3 +34,4 @@ class NativeTrace(ExeTracer):
abstract = True
type = 'NativeTrace'
cxx_class = 'Trace::NativeTrace'
+ cxx_header = "cpu/nativetrace.hh"
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
index 119de7f1c..811549bae 100644
--- a/src/cpu/inorder/InOrderCPU.py
+++ b/src/cpu/inorder/InOrderCPU.py
@@ -35,6 +35,7 @@ class ThreadModel(Enum):
class InOrderCPU(BaseCPU):
type = 'InOrderCPU'
+ cxx_header = "cpu/inorder/cpu.hh"
activity = Param.Unsigned(0, "Initial count")
threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
diff --git a/src/cpu/inorder/InOrderTrace.py b/src/cpu/inorder/InOrderTrace.py
index 3453fa675..fd4e00ed1 100644
--- a/src/cpu/inorder/InOrderTrace.py
+++ b/src/cpu/inorder/InOrderTrace.py
@@ -33,3 +33,4 @@ from InstTracer import InstTracer
class InOrderTrace(InstTracer):
type = 'InOrderTrace'
cxx_class = 'Trace::InOrderTrace'
+ cxx_header = "cpu/inorder/inorder_trace.hh"
diff --git a/src/cpu/inteltrace.hh b/src/cpu/inteltrace.hh
index dbb6300ac..e5f88bf1a 100644
--- a/src/cpu/inteltrace.hh
+++ b/src/cpu/inteltrace.hh
@@ -35,13 +35,12 @@
#include "base/trace.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
#include "debug/ExecEnable.hh"
#include "debug/ExecSpeculative.hh"
#include "params/IntelTrace.hh"
#include "sim/insttracer.hh"
-class ThreadContext;
-
namespace Trace {
class IntelTraceRecord : public InstRecord
diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py
index 1d3afbc6b..0f4ea67c7 100644
--- a/src/cpu/o3/FUPool.py
+++ b/src/cpu/o3/FUPool.py
@@ -33,6 +33,7 @@ from FuncUnitConfig import *
class FUPool(SimObject):
type = 'FUPool'
+ cxx_header = "cpu/o3/fu_pool.hh"
FUList = VectorParam.FUDesc("list of FU's for this pool")
class DefaultFUPool(FUPool):
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 54daaec63..1927a5862 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -43,6 +43,7 @@ from BaseSimpleCPU import BaseSimpleCPU
class AtomicSimpleCPU(BaseSimpleCPU):
type = 'AtomicSimpleCPU'
+ cxx_header = "cpu/simple/atomic.hh"
width = Param.Int(1, "CPU width")
simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py
index d9b963890..a4ae7e34b 100644
--- a/src/cpu/simple/BaseSimpleCPU.py
+++ b/src/cpu/simple/BaseSimpleCPU.py
@@ -34,6 +34,7 @@ from DummyChecker import DummyChecker
class BaseSimpleCPU(BaseCPU):
type = 'BaseSimpleCPU'
abstract = True
+ cxx_header = "cpu/simple/base.hh"
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index 61491b087..72560366e 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -31,3 +31,4 @@ from BaseSimpleCPU import BaseSimpleCPU
class TimingSimpleCPU(BaseSimpleCPU):
type = 'TimingSimpleCPU'
+ cxx_header = "cpu/simple/timing.hh"
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index db2cd817d..507decbdf 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -42,13 +42,13 @@
#include "config/the_isa.hh"
#include "cpu/op_class.hh"
#include "cpu/static_inst_fwd.hh"
+#include "cpu/thread_context.hh"
#include "sim/fault_fwd.hh"
// forward declarations
struct AlphaSimpleImpl;
struct OzoneImpl;
struct SimpleImpl;
-class ThreadContext;
class DynInst;
class Packet;
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py
index bf3eace08..f6a625735 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.py
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.py
@@ -34,20 +34,24 @@ from m5.proxy import *
class DirectedGenerator(SimObject):
type = 'DirectedGenerator'
abstract = True
+ cxx_header = "cpu/testers/directedtest/DirectedGenerator.hh"
num_cpus = Param.Int("num of cpus")
system = Param.System(Parent.any, "System we belong to")
class SeriesRequestGenerator(DirectedGenerator):
type = 'SeriesRequestGenerator'
+ cxx_header = "cpu/testers/directedtest/SeriesRequestGenerator.hh"
addr_increment_size = Param.Int(64, "address increment size")
issue_writes = Param.Bool(True, "issue writes if true, otherwise reads")
class InvalidateGenerator(DirectedGenerator):
type = 'InvalidateGenerator'
+ cxx_header = "cpu/testers/directedtest/InvalidateGenerator.hh"
addr_increment_size = Param.Int(64, "address increment size")
class RubyDirectedTester(MemObject):
type = 'RubyDirectedTester'
+ cxx_header = "cpu/testers/directedtest/RubyDirectedTester.hh"
cpuPort = VectorMasterPort("the cpu ports")
requests_to_complete = Param.Int("checks to complete")
generator = Param.DirectedGenerator("the request generator")
diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py
index 1b4d6767c..ad3ee9233 100644
--- a/src/cpu/testers/memtest/MemTest.py
+++ b/src/cpu/testers/memtest/MemTest.py
@@ -32,6 +32,7 @@ from m5.proxy import *
class MemTest(MemObject):
type = 'MemTest'
+ cxx_header = "cpu/testers/memtest/memtest.hh"
max_loads = Param.Counter(0, "number of loads to execute")
atomic = Param.Bool(False, "Execute tester in atomic mode? (or timing)\n")
memory_size = Param.Int(65536, "memory size")
diff --git a/src/cpu/testers/networktest/NetworkTest.py b/src/cpu/testers/networktest/NetworkTest.py
index 7d6ed576b..25b2bb690 100644
--- a/src/cpu/testers/networktest/NetworkTest.py
+++ b/src/cpu/testers/networktest/NetworkTest.py
@@ -32,6 +32,7 @@ from m5.proxy import *
class NetworkTest(MemObject):
type = 'NetworkTest'
+ cxx_header = "cpu/testers/networktest/networktest.hh"
block_offset = Param.Int(6, "block offset in bits")
num_memories = Param.Int(1, "Num Memories")
memory_size = Param.Int(65536, "memory size")
diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py
index 2eaeb8efd..7af70cae0 100644
--- a/src/cpu/testers/rubytest/RubyTester.py
+++ b/src/cpu/testers/rubytest/RubyTester.py
@@ -32,6 +32,7 @@ from m5.proxy import *
class RubyTester(MemObject):
type = 'RubyTester'
+ cxx_header = "cpu/testers/rubytest/RubyTester.hh"
num_cpus = Param.Int("number of cpus / RubyPorts")
cpuDataPort = VectorMasterPort("the cpu data cache ports")
cpuInstPort = VectorMasterPort("the cpu inst cache ports")
diff --git a/src/cpu/testers/traffic_gen/TrafficGen.py b/src/cpu/testers/traffic_gen/TrafficGen.py
index 15e9d7a9b..916279f91 100644
--- a/src/cpu/testers/traffic_gen/TrafficGen.py
+++ b/src/cpu/testers/traffic_gen/TrafficGen.py
@@ -61,6 +61,7 @@ from MemObject import MemObject
# probabilities, effectively making it a Markov Chain.
class TrafficGen(MemObject):
type = 'TrafficGen'
+ cxx_header = "cpu/testers/traffic_gen/traffic_gen.hh"
# Port used for sending requests and receiving responses
port = MasterPort("Master port")
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-07 09:54:29 +0000