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-rw-r--r--src/cpu/base.cc2
-rw-r--r--src/cpu/memtest/memtest.cc158
-rw-r--r--src/cpu/memtest/memtest.hh16
-rw-r--r--src/cpu/o3/commit_impl.hh2
-rw-r--r--src/cpu/o3/cpu.cc6
-rw-r--r--src/cpu/o3/fetch_impl.hh6
-rw-r--r--src/cpu/o3/inst_queue_impl.hh2
-rw-r--r--src/cpu/o3/lsq_unit.hh11
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh32
-rw-r--r--src/cpu/ozone/back_end_impl.hh4
-rw-r--r--src/cpu/ozone/cpu_impl.hh2
-rw-r--r--src/cpu/ozone/inorder_back_end_impl.hh2
-rw-r--r--src/cpu/ozone/inst_queue_impl.hh2
-rw-r--r--src/cpu/ozone/lsq_unit_impl.hh2
-rw-r--r--src/cpu/ozone/lw_back_end_impl.hh2
-rw-r--r--src/cpu/ozone/lw_lsq.hh16
-rw-r--r--src/cpu/ozone/lw_lsq_impl.hh25
-rw-r--r--src/cpu/quiesce_event.cc2
-rw-r--r--src/cpu/simple/atomic.cc96
-rw-r--r--src/cpu/simple/atomic.hh10
-rw-r--r--src/cpu/simple/base.hh3
-rw-r--r--src/cpu/simple/timing.cc42
-rw-r--r--src/cpu/simple/timing.hh6
-rw-r--r--src/cpu/trace/opt_cpu.cc2
-rw-r--r--src/cpu/trace/trace_cpu.cc2
25 files changed, 136 insertions, 317 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index f86313da0..cf007a06b 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -91,7 +91,7 @@ CPUProgressEvent::process()
const char *
CPUProgressEvent::description()
{
- return "CPU Progress event";
+ return "CPU Progress";
}
#if FULL_SYSTEM
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 15774904a..019b4328c 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -102,7 +102,6 @@ void
MemTest::sendPkt(PacketPtr pkt) {
if (atomic) {
cachePort.sendAtomic(pkt);
- pkt->makeAtomicResponse();
completeRequest(pkt);
}
else if (!cachePort.sendTiming(pkt)) {
@@ -165,8 +164,6 @@ MemTest::MemTest(const string &name,
tickEvent.schedule(0);
id = TESTER_ALLOCATOR++;
- if (TESTER_ALLOCATOR > 8)
- panic("False sharing memtester only allows up to 8 testers");
accessRetry = false;
}
@@ -194,29 +191,25 @@ MemTest::init()
// memory should be 0; no need to initialize them.
}
-static void
-printData(ostream &os, uint8_t *data, int nbytes)
-{
- os << hex << setfill('0');
- // assume little-endian: print bytes from highest address to lowest
- for (uint8_t *dp = data + nbytes - 1; dp >= data; --dp) {
- os << setw(2) << (unsigned)*dp;
- }
- os << dec;
-}
void
MemTest::completeRequest(PacketPtr pkt)
{
+ Request *req = pkt->req;
+
+ DPRINTF(MemTest, "completing %s at address %x (blk %x)\n",
+ pkt->isWrite() ? "write" : "read",
+ req->getPaddr(), blockAddr(req->getPaddr()));
+
MemTestSenderState *state =
dynamic_cast<MemTestSenderState *>(pkt->senderState);
uint8_t *data = state->data;
uint8_t *pkt_data = pkt->getPtr<uint8_t>();
- Request *req = pkt->req;
//Remove the address from the list of outstanding
- std::set<unsigned>::iterator removeAddr = outstandingAddrs.find(req->getPaddr());
+ std::set<unsigned>::iterator removeAddr =
+ outstandingAddrs.find(req->getPaddr());
assert(removeAddr != outstandingAddrs.end());
outstandingAddrs.erase(removeAddr);
@@ -224,15 +217,10 @@ MemTest::completeRequest(PacketPtr pkt)
case MemCmd::ReadResp:
if (memcmp(pkt_data, data, pkt->getSize()) != 0) {
- cerr << name() << ": on read of 0x" << hex << req->getPaddr()
- << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
- << "@ cycle " << dec << curTick
- << ", cache returns 0x";
- printData(cerr, pkt_data, pkt->getSize());
- cerr << ", expected 0x";
- printData(cerr, data, pkt->getSize());
- cerr << endl;
- fatal("");
+ panic("%s: read of %x (blk %x) @ cycle %d "
+ "returns %x, expected %x\n", name(),
+ req->getPaddr(), blockAddr(req->getPaddr()), curTick,
+ *pkt_data, *data);
}
numReads++;
@@ -245,39 +233,17 @@ MemTest::completeRequest(PacketPtr pkt)
}
if (numReads >= maxLoads)
- exitSimLoop("Maximum number of loads reached!");
+ exitSimLoop("maximum number of loads reached");
break;
case MemCmd::WriteResp:
numWritesStat++;
break;
-/*
- case Copy:
- //Also remove dest from outstanding list
- removeAddr = outstandingAddrs.find(req->dest);
- assert(removeAddr != outstandingAddrs.end());
- outstandingAddrs.erase(removeAddr);
- numCopiesStat++;
- break;
-*/
+
default:
panic("invalid command %s (%d)", pkt->cmdString(), pkt->cmd.toInt());
}
- if (blockAddr(req->getPaddr()) == traceBlockAddr) {
- cerr << name() << ": completed "
- << (pkt->isWrite() ? "write" : "read")
- << " access of "
- << dec << pkt->getSize() << " bytes at address 0x"
- << hex << req->getPaddr()
- << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
- << ", value = 0x";
- printData(cerr, pkt_data, pkt->getSize());
- cerr << " @ cycle " << dec << curTick;
-
- cerr << endl;
- }
-
noResponseCycles = 0;
delete state;
delete [] data;
@@ -333,7 +299,7 @@ MemTest::tick()
//mem tester
//We can eliminate the lower bits of the offset, and then use the id
//to offset within the blks
- offset &= ~63; //Not the low order bits
+ offset = blockAddr(offset);
offset += id;
access_size = 0;
@@ -359,31 +325,26 @@ MemTest::tick()
if (cmd < percentReads) {
// read
- //For now we only allow one outstanding request per addreess per tester
- //This means we assume CPU does write forwarding to reads that alias something
- //in the cpu store buffer.
+ // For now we only allow one outstanding request per address
+ // per tester This means we assume CPU does write forwarding
+ // to reads that alias something in the cpu store buffer.
if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
delete [] result;
delete req;
return;
}
- else outstandingAddrs.insert(paddr);
+
+ outstandingAddrs.insert(paddr);
// ***** NOTE FOR RON: I'm not sure how to access checkMem. - Kevin
funcPort.readBlob(req->getPaddr(), result, req->getSize());
- if (blockAddr(paddr) == traceBlockAddr) {
- cerr << name()
- << ": initiating read "
- << ((probe) ? "probe of " : "access of ")
- << dec << req->getSize() << " bytes from addr 0x"
- << hex << paddr
- << " (0x" << hex << blockAddr(paddr) << ")"
- << " at cycle "
- << dec << curTick << endl;
- }
+ DPRINTF(MemTest,
+ "initiating read at address %x (blk %x) expecting %x\n",
+ req->getPaddr(), blockAddr(req->getPaddr()), *result);
PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+ pkt->setSrc(0);
pkt->dataDynamicArray(new uint8_t[req->getSize()]);
MemTestSenderState *state = new MemTestSenderState(result);
pkt->senderState = state;
@@ -393,37 +354,27 @@ MemTest::tick()
pkt->makeAtomicResponse();
completeRequest(pkt);
} else {
-// req->completionEvent = new MemCompleteEvent(req, result, this);
sendPkt(pkt);
}
} else {
// write
- //For now we only allow one outstanding request per addreess per tester
- //This means we assume CPU does write forwarding to reads that alias something
- //in the cpu store buffer.
+ // For now we only allow one outstanding request per addreess
+ // per tester. This means we assume CPU does write forwarding
+ // to reads that alias something in the cpu store buffer.
if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
delete [] result;
delete req;
return;
}
- else outstandingAddrs.insert(paddr);
+ outstandingAddrs.insert(paddr);
+
+ DPRINTF(MemTest, "initiating write at address %x (blk %x) value %x\n",
+ req->getPaddr(), blockAddr(req->getPaddr()), data & 0xff);
-/*
- if (blockAddr(req->getPaddr()) == traceBlockAddr) {
- cerr << name() << ": initiating write "
- << ((probe)?"probe of ":"access of ")
- << dec << req->getSize() << " bytes (value = 0x";
- printData(cerr, data_pkt->getPtr(), req->getSize());
- cerr << ") to addr 0x"
- << hex << req->getPaddr()
- << " (0x" << hex << blockAddr(req->getPaddr()) << ")"
- << " at cycle "
- << dec << curTick << endl;
- }
-*/
PacketPtr pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
+ pkt->setSrc(0);
uint8_t *pkt_data = new uint8_t[req->getSize()];
pkt->dataDynamicArray(pkt_data);
memcpy(pkt_data, &data, req->getSize());
@@ -437,54 +388,9 @@ MemTest::tick()
pkt->makeAtomicResponse();
completeRequest(pkt);
} else {
-// req->completionEvent = new MemCompleteEvent(req, NULL, this);
sendPkt(pkt);
}
}
-/* else {
- // copy
- unsigned source_align = random() % 100;
- unsigned dest_align = random() % 100;
- unsigned offset2 = random() % size;
-
- Addr source = ((base) ? baseAddr1 : baseAddr2) + offset;
- Addr dest = ((base) ? baseAddr2 : baseAddr1) + offset2;
- if (outstandingAddrs.find(source) != outstandingAddrs.end()) return;
- else outstandingAddrs.insert(source);
- if (outstandingAddrs.find(dest) != outstandingAddrs.end()) return;
- else outstandingAddrs.insert(dest);
-
- if (source_align >= percentSourceUnaligned) {
- source = blockAddr(source);
- }
- if (dest_align >= percentDestUnaligned) {
- dest = blockAddr(dest);
- }
- req->cmd = Copy;
- req->flags &= ~UNCACHEABLE;
- req->paddr = source;
- req->dest = dest;
- delete [] req->data;
- req->data = new uint8_t[blockSize];
- req->size = blockSize;
- if (source == traceBlockAddr || dest == traceBlockAddr) {
- cerr << name()
- << ": initiating copy of "
- << dec << req->size << " bytes from addr 0x"
- << hex << source
- << " (0x" << hex << blockAddr(source) << ")"
- << " to addr 0x"
- << hex << dest
- << " (0x" << hex << blockAddr(dest) << ")"
- << " at cycle "
- << dec << curTick << endl;
- }*
- cacheInterface->access(req);
- uint8_t result[blockSize];
- checkMem->access(Read, source, &result, blockSize);
- checkMem->access(Write, dest, &result, blockSize);
- }
-*/
}
void
diff --git a/src/cpu/memtest/memtest.hh b/src/cpu/memtest/memtest.hh
index 123ee2a6c..f4713709a 100644
--- a/src/cpu/memtest/memtest.hh
+++ b/src/cpu/memtest/memtest.hh
@@ -35,8 +35,6 @@
#include <set>
#include "base/statistics.hh"
-//#include "mem/functional/functional.hh"
-//#include "mem/mem_interface.hh"
#include "sim/eventq.hh"
#include "sim/sim_exit.hh"
#include "sim/sim_object.hh"
@@ -50,9 +48,6 @@ class MemTest : public MemObject
public:
MemTest(const std::string &name,
-// MemInterface *_cache_interface,
-// PhysicalMemory *main_mem,
-// PhysicalMemory *check_mem,
unsigned _memorySize,
unsigned _percentReads,
unsigned _percentFunctional,
@@ -85,13 +80,13 @@ class MemTest : public MemObject
TickEvent(MemTest *c)
: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {}
void process() {cpu->tick();}
- virtual const char *description() { return "tick event"; }
+ virtual const char *description() { return "MemTest tick"; }
};
TickEvent tickEvent;
+
class CpuPort : public Port
{
-
MemTest *memtest;
public:
@@ -116,7 +111,7 @@ class MemTest : public MemObject
virtual void getDeviceAddressRanges(AddrRangeList &resp,
bool &snoop)
- { resp.clear(); snoop = true; }
+ { resp.clear(); snoop = false; }
};
CpuPort cachePort;
@@ -136,12 +131,7 @@ class MemTest : public MemObject
uint8_t *data;
};
-// Request *dataReq;
PacketPtr retryPkt;
-// MemInterface *cacheInterface;
-// PhysicalMemory *mainMem;
-// PhysicalMemory *checkMem;
-// SimpleThread *thread;
bool accessRetry;
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 9411c6c62..f263383ae 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -67,7 +67,7 @@ template <class Impl>
const char *
DefaultCommit<Impl>::TrapEvent::description()
{
- return "Trap event";
+ return "Trap";
}
template <class Impl>
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 6a3eb9c43..2bf8f9832 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -83,7 +83,7 @@ template <class Impl>
const char *
FullO3CPU<Impl>::TickEvent::description()
{
- return "FullO3CPU tick event";
+ return "FullO3CPU tick";
}
template <class Impl>
@@ -112,7 +112,7 @@ template <class Impl>
const char *
FullO3CPU<Impl>::ActivateThreadEvent::description()
{
- return "FullO3CPU \"Activate Thread\" event";
+ return "FullO3CPU \"Activate Thread\"";
}
template <class Impl>
@@ -144,7 +144,7 @@ template <class Impl>
const char *
FullO3CPU<Impl>::DeallocateContextEvent::description()
{
- return "FullO3CPU \"Deallocate Context\" event";
+ return "FullO3CPU \"Deallocate Context\"";
}
template <class Impl>
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 01e9b5b31..aa0c69ac4 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -628,12 +628,6 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
// Now do the timing access to see whether or not the instruction
// exists within the cache.
if (!icachePort->sendTiming(data_pkt)) {
- if (data_pkt->result == Packet::BadAddress) {
- fault = TheISA::genMachineCheckFault();
- delete mem_req;
- memReq[tid] = NULL;
- warn("Bad address!\n");
- }
assert(retryPkt == NULL);
assert(retryTid == -1);
DPRINTF(Fetch, "[tid:%i] Out of MSHRs!\n", tid);
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index bdf5f07aa..99bffe1a6 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -60,7 +60,7 @@ template <class Impl>
const char *
InstructionQueue<Impl>::FUCompletion::description()
{
- return "Functional unit completion event";
+ return "Functional unit completion";
}
template <class Impl>
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index cc33e025d..be9224099 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -643,7 +643,10 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
// if we the cache is not blocked, do cache access
if (!lsq->cacheBlocked()) {
PacketPtr data_pkt =
- new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+ new Packet(req,
+ (req->isLocked() ?
+ MemCmd::LoadLockedReq : MemCmd::ReadReq),
+ Packet::Broadcast);
data_pkt->dataStatic(load_inst->memData);
LSQSenderState *state = new LSQSenderState;
@@ -653,8 +656,6 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
data_pkt->senderState = state;
if (!dcachePort->sendTiming(data_pkt)) {
- Packet::Result result = data_pkt->result;
-
// Delete state and data packet because a load retry
// initiates a pipeline restart; it does not retry.
delete state;
@@ -663,10 +664,6 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
req = NULL;
- if (result == Packet::BadAddress) {
- return TheISA::genMachineCheckFault();
- }
-
// If the access didn't succeed, tell the LSQ by setting
// the retry thread id.
lsq->setRetryTid(lsqID);
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index bde4f8079..5ae1cc0e4 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -69,7 +69,7 @@ template<class Impl>
const char *
LSQUnit<Impl>::WritebackEvent::description()
{
- return "Store writeback event";
+ return "Store writeback";
}
template<class Impl>
@@ -647,7 +647,9 @@ LSQUnit<Impl>::writebackStores()
memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
- MemCmd command = req->isSwap() ? MemCmd::SwapReq : MemCmd::WriteReq;
+ MemCmd command =
+ req->isSwap() ? MemCmd::SwapReq :
+ (req->isLocked() ? MemCmd::WriteReq : MemCmd::StoreCondReq);
PacketPtr data_pkt = new Packet(req, command,
Packet::Broadcast);
data_pkt->dataStatic(inst->memData);
@@ -690,9 +692,6 @@ LSQUnit<Impl>::writebackStores()
}
if (!dcachePort->sendTiming(data_pkt)) {
- if (data_pkt->result == Packet::BadAddress) {
- panic("LSQ sent out a bad address for a completed store!");
- }
// Need to handle becoming blocked on a store.
DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will"
"retry later\n",
@@ -844,26 +843,6 @@ LSQUnit<Impl>::storePostSend(PacketPtr pkt)
#endif
}
- if (pkt->result != Packet::Success) {
- DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
- storeWBIdx);
-
- DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
- storeQueue[storeWBIdx].inst->seqNum);
-
- //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
-
- //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
-
- // @todo: Increment stat here.
- } else {
- DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
- storeWBIdx);
-
- DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
- storeQueue[storeWBIdx].inst->seqNum);
- }
-
incrStIdx(storeWBIdx);
}
@@ -952,9 +931,6 @@ LSQUnit<Impl>::recvRetry()
assert(retryPkt != NULL);
if (dcachePort->sendTiming(retryPkt)) {
- if (retryPkt->result == Packet::BadAddress) {
- panic("LSQ sent out a bad address for a completed store!");
- }
storePostSend(retryPkt);
retryPkt = NULL;
isStoreBlocked = false;
diff --git a/src/cpu/ozone/back_end_impl.hh b/src/cpu/ozone/back_end_impl.hh
index 4078699fe..27146ecf0 100644
--- a/src/cpu/ozone/back_end_impl.hh
+++ b/src/cpu/ozone/back_end_impl.hh
@@ -583,7 +583,7 @@ template<class Impl>
const char *
BackEnd<Impl>::LdWritebackEvent::description()
{
- return "Load writeback event";
+ return "Load writeback";
}
@@ -603,7 +603,7 @@ template <class Impl>
const char *
BackEnd<Impl>::DCacheCompletionEvent::description()
{
- return "Cache completion event";
+ return "Cache completion";
}
template <class Impl>
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index d1214223b..d73e5768a 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -84,7 +84,7 @@ template <class Impl>
const char *
OzoneCPU<Impl>::TickEvent::description()
{
- return "OzoneCPU tick event";
+ return "OzoneCPU tick";
}
template <class Impl>
diff --git a/src/cpu/ozone/inorder_back_end_impl.hh b/src/cpu/ozone/inorder_back_end_impl.hh
index 8d7ebb60e..c57fa0200 100644
--- a/src/cpu/ozone/inorder_back_end_impl.hh
+++ b/src/cpu/ozone/inorder_back_end_impl.hh
@@ -540,5 +540,5 @@ template <class Impl>
const char *
InorderBackEnd<Impl>::DCacheCompletionEvent::description()
{
- return "DCache completion event";
+ return "DCache completion";
}
diff --git a/src/cpu/ozone/inst_queue_impl.hh b/src/cpu/ozone/inst_queue_impl.hh
index ea9d03c0d..461c7eb0f 100644
--- a/src/cpu/ozone/inst_queue_impl.hh
+++ b/src/cpu/ozone/inst_queue_impl.hh
@@ -64,7 +64,7 @@ template <class Impl>
const char *
InstQueue<Impl>::FUCompletion::description()
{
- return "Functional unit completion event";
+ return "Functional unit completion";
}
#endif
template <class Impl>
diff --git a/src/cpu/ozone/lsq_unit_impl.hh b/src/cpu/ozone/lsq_unit_impl.hh
index c46eb90be..e08e54835 100644
--- a/src/cpu/ozone/lsq_unit_impl.hh
+++ b/src/cpu/ozone/lsq_unit_impl.hh
@@ -62,7 +62,7 @@ template <class Impl>
const char *
OzoneLSQ<Impl>::StoreCompletionEvent::description()
{
- return "LSQ store completion event";
+ return "LSQ store completion";
}
template <class Impl>
diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh
index c0a9cad24..f84bda348 100644
--- a/src/cpu/ozone/lw_back_end_impl.hh
+++ b/src/cpu/ozone/lw_back_end_impl.hh
@@ -121,7 +121,7 @@ template <class Impl>
const char *
LWBackEnd<Impl>::TrapEvent::description()
{
- return "Trap event";
+ return "Trap";
}
template <class Impl>
diff --git a/src/cpu/ozone/lw_lsq.hh b/src/cpu/ozone/lw_lsq.hh
index 2048ad6bb..ba40e9ce1 100644
--- a/src/cpu/ozone/lw_lsq.hh
+++ b/src/cpu/ozone/lw_lsq.hh
@@ -632,7 +632,11 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
DPRINTF(OzoneLSQ, "Doing timing access for inst PC %#x\n",
inst->readPC());
- PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+ PacketPtr data_pkt =
+ new Packet(req,
+ (req->isLocked() ?
+ MemCmd::LoadLockedReq : Packet::ReadReq),
+ Packet::Broadcast);
data_pkt->dataStatic(inst->memData);
LSQSenderState *state = new LSQSenderState;
@@ -661,16 +665,6 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
cpu->lockFlag = true;
}
- if (data_pkt->result != Packet::Success) {
- DPRINTF(OzoneLSQ, "OzoneLSQ: D-cache miss!\n");
- DPRINTF(Activity, "Activity: ld accessing mem miss [sn:%lli]\n",
- inst->seqNum);
- } else {
- DPRINTF(OzoneLSQ, "OzoneLSQ: D-cache hit!\n");
- DPRINTF(Activity, "Activity: ld accessing mem hit [sn:%lli]\n",
- inst->seqNum);
- }
-
return NoFault;
}
diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh
index f26b06453..82191312a 100644
--- a/src/cpu/ozone/lw_lsq_impl.hh
+++ b/src/cpu/ozone/lw_lsq_impl.hh
@@ -57,7 +57,7 @@ template<class Impl>
const char *
OzoneLWLSQ<Impl>::WritebackEvent::description()
{
- return "Store writeback event";
+ return "Store writeback";
}
template <class Impl>
@@ -587,7 +587,10 @@ OzoneLWLSQ<Impl>::writebackStores()
memcpy(inst->memData, (uint8_t *)&(*sq_it).data,
req->getSize());
- PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
+ MemCmd command =
+ req->isSwap() ? MemCmd::SwapReq :
+ (req->isLocked() ? MemCmd::WriteReq : MemCmd::StoreCondReq);
+ PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast);
data_pkt->dataStatic(inst->memData);
LSQSenderState *state = new LSQSenderState;
@@ -853,24 +856,6 @@ OzoneLWLSQ<Impl>::storePostSend(PacketPtr pkt, DynInstPtr &inst)
}
#endif
}
-
- if (pkt->result != Packet::Success) {
- DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
-
- DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
- inst->seqNum);
-
- //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
-
- //DPRINTF(OzoneLWLSQ, "Added MSHR. count = %i\n",mshrSeqNums.size());
-
- // @todo: Increment stat here.
- } else {
- DPRINTF(OzoneLSQ,"D-Cache: Write Hit!\n");
-
- DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
- inst->seqNum);
- }
}
template <class Impl>
diff --git a/src/cpu/quiesce_event.cc b/src/cpu/quiesce_event.cc
index fa79e6d1e..3495a0e52 100644
--- a/src/cpu/quiesce_event.cc
+++ b/src/cpu/quiesce_event.cc
@@ -47,5 +47,5 @@ EndQuiesceEvent::process()
const char*
EndQuiesceEvent::description()
{
- return "End Quiesce Event.";
+ return "End Quiesce";
}
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 03ff1282b..01eb4873e 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -57,7 +57,7 @@ AtomicSimpleCPU::TickEvent::process()
const char *
AtomicSimpleCPU::TickEvent::description()
{
- return "AtomicSimpleCPU tick event";
+ return "AtomicSimpleCPU tick";
}
Port *
@@ -148,23 +148,9 @@ AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
icachePort.snoopRangeSent = false;
dcachePort.snoopRangeSent = false;
- ifetch_req = new Request();
- ifetch_req->setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
- ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
- ifetch_pkt->dataStatic(&inst);
-
- data_read_req = new Request();
- data_read_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
- data_read_pkt = new Packet(data_read_req, MemCmd::ReadReq,
- Packet::Broadcast);
- data_read_pkt->dataStatic(&dataReg);
-
- data_write_req = new Request();
- data_write_req->setThreadContext(p->cpu_id, 0); // Add thread ID here too
- data_write_pkt = new Packet(data_write_req, MemCmd::WriteReq,
- Packet::Broadcast);
- data_swap_pkt = new Packet(data_write_req, MemCmd::SwapReq,
- Packet::Broadcast);
+ ifetch_req.setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
+ data_read_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
+ data_write_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
}
@@ -282,9 +268,7 @@ Fault
AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
{
// use the CPU's statically allocated read request and packet objects
- Request *req = data_read_req;
- PacketPtr pkt = data_read_pkt;
-
+ Request *req = &data_read_req;
req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
if (traceData) {
@@ -296,19 +280,18 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
// Now do the access.
if (fault == NoFault) {
- pkt->reinitFromRequest();
+ Packet pkt =
+ Packet(req,
+ req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
+ Packet::Broadcast);
+ pkt.dataStatic(&data);
if (req->isMmapedIpr())
- dcache_latency = TheISA::handleIprRead(thread->getTC(),pkt);
+ dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
else
- dcache_latency = dcachePort.sendAtomic(pkt);
+ dcache_latency = dcachePort.sendAtomic(&pkt);
dcache_access = true;
-#if !defined(NDEBUG)
- if (pkt->result != Packet::Success)
- panic("Unable to find responder for address pa = %#X va = %#X\n",
- pkt->req->getPaddr(), pkt->req->getVaddr());
-#endif
- data = pkt->get<T>();
+ assert(!pkt.isError());
if (req->isLocked()) {
TheISA::handleLockedRead(thread, req);
@@ -378,16 +361,9 @@ Fault
AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
{
// use the CPU's statically allocated write request and packet objects
- Request *req = data_write_req;
- PacketPtr pkt;
-
+ Request *req = &data_write_req;
req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
- if (req->isSwap())
- pkt = data_swap_pkt;
- else
- pkt = data_write_pkt;
-
if (traceData) {
traceData->setAddr(addr);
}
@@ -397,40 +373,40 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
// Now do the access.
if (fault == NoFault) {
+ MemCmd cmd = MemCmd::WriteReq; // default
bool do_access = true; // flag to suppress cache access
if (req->isLocked()) {
+ cmd = MemCmd::StoreCondReq;
do_access = TheISA::handleLockedWrite(thread, req);
+ } else if (req->isSwap()) {
+ cmd = MemCmd::SwapReq;
+ if (req->isCondSwap()) {
+ assert(res);
+ req->setExtraData(*res);
+ }
}
- if (req->isCondSwap()) {
- assert(res);
- req->setExtraData(*res);
- }
-
if (do_access) {
- pkt->reinitFromRequest();
- pkt->dataStatic(&data);
+ Packet pkt = Packet(req, cmd, Packet::Broadcast);
+ pkt.dataStatic(&data);
if (req->isMmapedIpr()) {
- dcache_latency = TheISA::handleIprWrite(thread->getTC(), pkt);
+ dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
} else {
data = htog(data);
- dcache_latency = dcachePort.sendAtomic(pkt);
+ dcache_latency = dcachePort.sendAtomic(&pkt);
}
dcache_access = true;
+ assert(!pkt.isError());
-#if !defined(NDEBUG)
- if (pkt->result != Packet::Success)
- panic("Unable to find responder for address pa = %#X va = %#X\n",
- pkt->req->getPaddr(), pkt->req->getVaddr());
-#endif
+ if (req->isSwap()) {
+ assert(res);
+ *res = pkt.get<T>();
+ }
}
- if (req->isSwap()) {
- assert(res);
- *res = pkt->get<T>();
- } else if (res) {
+ if (res && !req->isSwap()) {
*res = req->getExtraData();
}
}
@@ -513,7 +489,7 @@ AtomicSimpleCPU::tick()
if (!curStaticInst || !curStaticInst->isDelayedCommit())
checkForInterrupts();
- Fault fault = setupFetchRequest(ifetch_req);
+ Fault fault = setupFetchRequest(&ifetch_req);
if (fault == NoFault) {
Tick icache_latency = 0;
@@ -524,9 +500,11 @@ AtomicSimpleCPU::tick()
//if(predecoder.needMoreBytes())
//{
icache_access = true;
- ifetch_pkt->reinitFromRequest();
+ Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
+ Packet::Broadcast);
+ ifetch_pkt.dataStatic(&inst);
- icache_latency = icachePort.sendAtomic(ifetch_pkt);
+ icache_latency = icachePort.sendAtomic(&ifetch_pkt);
// ifetch_req is initialized to read the instruction directly
// into the CPU object's inst field.
//}
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index b127e3791..28e883b24 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -121,13 +121,9 @@ class AtomicSimpleCPU : public BaseSimpleCPU
};
DcachePort dcachePort;
- Request *ifetch_req;
- PacketPtr ifetch_pkt;
- Request *data_read_req;
- PacketPtr data_read_pkt;
- Request *data_write_req;
- PacketPtr data_write_pkt;
- PacketPtr data_swap_pkt;
+ Request ifetch_req;
+ Request data_read_req;
+ Request data_write_req;
bool dcache_access;
Tick dcache_latency;
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 243167db0..0550aa036 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -131,9 +131,6 @@ class BaseSimpleCPU : public BaseCPU
// The predecoder
TheISA::Predecoder predecoder;
- // Static data storage
- TheISA::LargestRead dataReg;
-
StaticInstPtr curStaticInst;
StaticInstPtr curMacroStaticInst;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 7698a588d..0c03815b5 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -260,7 +260,10 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
// Now do the access.
if (fault == NoFault) {
PacketPtr pkt =
- new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+ new Packet(req,
+ (req->isLocked() ?
+ MemCmd::LoadLockedReq : MemCmd::ReadReq),
+ Packet::Broadcast);
pkt->dataDynamic<T>(new T);
if (!dcachePort.sendTiming(pkt)) {
@@ -350,23 +353,26 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
// Now do the access.
if (fault == NoFault) {
- assert(dcache_pkt == NULL);
- if (req->isSwap())
- dcache_pkt = new Packet(req, MemCmd::SwapReq, Packet::Broadcast);
- else
- dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
- dcache_pkt->allocate();
- dcache_pkt->set(data);
-
+ MemCmd cmd = MemCmd::WriteReq; // default
bool do_access = true; // flag to suppress cache access
if (req->isLocked()) {
+ cmd = MemCmd::StoreCondReq;
do_access = TheISA::handleLockedWrite(thread, req);
+ } else if (req->isSwap()) {
+ cmd = MemCmd::SwapReq;
+ if (req->isCondSwap()) {
+ assert(res);
+ req->setExtraData(*res);
+ }
}
- if (req->isCondSwap()) {
- assert(res);
- req->setExtraData(*res);
- }
+
+ // Note: need to allocate dcache_pkt even if do_access is
+ // false, as it's used unconditionally to call completeAcc().
+ assert(dcache_pkt == NULL);
+ dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
+ dcache_pkt->allocate();
+ dcache_pkt->set(data);
if (do_access) {
if (!dcachePort.sendTiming(dcache_pkt)) {
@@ -501,7 +507,7 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
{
// received a response from the icache: execute the received
// instruction
- assert(pkt->result == Packet::Success);
+ assert(!pkt->isError());
assert(_status == IcacheWaitResponse);
_status = Running;
@@ -569,7 +575,7 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
return true;
}
- else if (pkt->result == Packet::Nacked) {
+ else if (pkt->wasNacked()) {
assert(cpu->_status == IcacheWaitResponse);
pkt->reinitNacked();
if (!sendTiming(pkt)) {
@@ -600,7 +606,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
{
// received a response from the dcache: complete the load or store
// instruction
- assert(pkt->result == Packet::Success);
+ assert(!pkt->isError());
assert(_status == DcacheWaitResponse);
_status = Running;
@@ -609,7 +615,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
- if (pkt->isRead() && pkt->req->isLocked()) {
+ if (pkt->isRead() && pkt->isLocked()) {
TheISA::handleLockedRead(thread, pkt->req);
}
@@ -663,7 +669,7 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
return true;
}
- else if (pkt->result == Packet::Nacked) {
+ else if (pkt->wasNacked()) {
assert(cpu->_status == DcacheWaitResponse);
pkt->reinitNacked();
if (!sendTiming(pkt)) {
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 39958bfb6..ba194b3fa 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -101,7 +101,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
TickEvent(TimingSimpleCPU *_cpu)
:Event(&mainEventQueue), cpu(_cpu) {}
- const char *description() { return "Timing CPU clock event"; }
+ const char *description() { return "Timing CPU tick"; }
void schedule(PacketPtr _pkt, Tick t);
};
@@ -127,7 +127,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
ITickEvent(TimingSimpleCPU *_cpu)
: TickEvent(_cpu) {}
void process();
- const char *description() { return "Timing CPU clock event"; }
+ const char *description() { return "Timing CPU icache tick"; }
};
ITickEvent tickEvent;
@@ -155,7 +155,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
DTickEvent(TimingSimpleCPU *_cpu)
: TickEvent(_cpu) {}
void process();
- const char *description() { return "Timing CPU clock event"; }
+ const char *description() { return "Timing CPU dcache tick"; }
};
DTickEvent tickEvent;
diff --git a/src/cpu/trace/opt_cpu.cc b/src/cpu/trace/opt_cpu.cc
index 996e89f01..0f2944f07 100644
--- a/src/cpu/trace/opt_cpu.cc
+++ b/src/cpu/trace/opt_cpu.cc
@@ -207,7 +207,7 @@ OptCPU::TickEvent::process()
const char *
OptCPU::TickEvent::description()
{
- return "OptCPU tick event";
+ return "OptCPU tick";
}
diff --git a/src/cpu/trace/trace_cpu.cc b/src/cpu/trace/trace_cpu.cc
index 3c9da4849..32ed6c7d7 100644
--- a/src/cpu/trace/trace_cpu.cc
+++ b/src/cpu/trace/trace_cpu.cc
@@ -148,7 +148,7 @@ TraceCPU::TickEvent::process()
const char *
TraceCPU::TickEvent::description()
{
- return "TraceCPU tick event";
+ return "TraceCPU tick";
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-26 18:39:02 +0000