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-rw-r--r--src/cpu/base.cc17
-rw-r--r--src/cpu/o3/fetch.hh4
-rw-r--r--src/cpu/o3/fetch_impl.hh2
-rw-r--r--src/cpu/o3/lsq.hh4
-rw-r--r--src/cpu/o3/lsq_impl.hh2
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh1
-rw-r--r--src/cpu/ozone/cpu_impl.hh1
-rw-r--r--src/cpu/simple/AtomicSimpleCPU.py3
-rw-r--r--src/cpu/simple/atomic.cc39
-rw-r--r--src/cpu/simple/atomic.hh6
-rw-r--r--src/cpu/simple_thread.cc6
-rw-r--r--src/cpu/thread_state.cc6
12 files changed, 47 insertions, 44 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 23195f720..6ce082996 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -351,22 +351,17 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
// Connect new CPU to old CPU's memory only if new CPU isn't
// connected to anything. Also connect old CPU's memory to new
// CPU.
- Port *peer;
- if (ic->getPeer() == NULL || ic->getPeer()->isDefaultPort()) {
- peer = oldCPU->getPort("icache_port")->getPeer();
+ if (!ic->isConnected()) {
+ Port *peer = oldCPU->getPort("icache_port")->getPeer();
ic->setPeer(peer);
- } else {
- peer = ic->getPeer();
+ peer->setPeer(ic);
}
- peer->setPeer(ic);
- if (dc->getPeer() == NULL || dc->getPeer()->isDefaultPort()) {
- peer = oldCPU->getPort("dcache_port")->getPeer();
+ if (!dc->isConnected()) {
+ Port *peer = oldCPU->getPort("dcache_port")->getPeer();
dc->setPeer(peer);
- } else {
- peer = dc->getPeer();
+ peer->setPeer(dc);
}
- peer->setPeer(dc);
}
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index d954bd1e7..3ada0328f 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -80,8 +80,8 @@ class DefaultFetch
public:
/** Default constructor. */
- IcachePort(DefaultFetch<Impl> *_fetch)
- : Port(_fetch->name() + "-iport"), fetch(_fetch)
+ IcachePort(DefaultFetch<Impl> *_fetch, O3CPU *_cpu)
+ : Port(_fetch->name() + "-iport", _cpu), fetch(_fetch)
{ }
bool snoopRangeSent;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 7d344fa33..ecfbacd98 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -167,7 +167,7 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, Params *params)
instSize = sizeof(TheISA::MachInst);
// Name is finally available, so create the port.
- icachePort = new IcachePort(this);
+ icachePort = new IcachePort(this, cpu);
icachePort->snoopRangeSent = false;
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 06de608e0..82d73c6ee 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -296,8 +296,8 @@ class LSQ {
public:
/** Default constructor. */
- DcachePort(LSQ *_lsq)
- : Port(_lsq->name() + "-dport"), lsq(_lsq)
+ DcachePort(LSQ *_lsq, O3CPU *_cpu)
+ : Port(_lsq->name() + "-dport", _cpu), lsq(_lsq)
{ }
bool snoopRangeSent;
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 8ed6f7f54..41ab66dd0 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -112,7 +112,7 @@ LSQ<Impl>::DcachePort::recvRetry()
template <class Impl>
LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params)
- : cpu(cpu_ptr), iewStage(iew_ptr), dcachePort(this),
+ : cpu(cpu_ptr), iewStage(iew_ptr), dcachePort(this, cpu_ptr),
LQEntries(params->LQEntries),
SQEntries(params->SQEntries),
numThreads(params->numberOfThreads),
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 865d58635..514d3de64 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -103,7 +103,6 @@ void
O3ThreadContext<Impl>::delVirtPort(VirtualPort *vp)
{
if (vp != thread->getVirtPort()) {
- vp->removeConn();
delete vp;
}
}
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 0c7105382..4cb55fa23 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -747,7 +747,6 @@ template <class Impl>
void
OzoneCPU<Impl>::OzoneTC::delVirtPort(VirtualPort *vp)
{
- vp->removeConn();
delete vp;
}
#endif
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 28c2aa9c9..a0b358439 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -33,7 +33,8 @@ from BaseCPU import BaseCPU
class AtomicSimpleCPU(BaseCPU):
type = 'AtomicSimpleCPU'
width = Param.Int(1, "CPU width")
- simulate_stalls = Param.Bool(False, "Simulate cache stall cycles")
+ simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
+ simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
if build_env['FULL_SYSTEM']:
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index acd280568..b25d3330f 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -153,8 +153,9 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port)
}
AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
- : BaseSimpleCPU(p), tickEvent(this),
- width(p->width), simulate_stalls(p->simulate_stalls),
+ : BaseSimpleCPU(p), tickEvent(this), width(p->width),
+ simulate_data_stalls(p->simulate_data_stalls),
+ simulate_inst_stalls(p->simulate_inst_stalls),
icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
physmemPort(name() + "-iport", this), hasPhysMemPort(false)
{
@@ -711,7 +712,7 @@ AtomicSimpleCPU::tick()
{
DPRINTF(SimpleCPU, "Tick\n");
- Tick latency = ticks(1); // instruction takes one cycle by default
+ Tick latency = 0;
for (int i = 0; i < width; ++i) {
numCycles++;
@@ -769,16 +770,21 @@ AtomicSimpleCPU::tick()
curStaticInst->isFirstMicroop()))
instCnt++;
- if (simulate_stalls) {
- Tick icache_stall =
- icache_access ? icache_latency - ticks(1) : 0;
- Tick dcache_stall =
- dcache_access ? dcache_latency - ticks(1) : 0;
- Tick stall_cycles = (icache_stall + dcache_stall) / ticks(1);
- if (ticks(stall_cycles) < (icache_stall + dcache_stall))
- latency += ticks(stall_cycles+1);
- else
- latency += ticks(stall_cycles);
+ Tick stall_ticks = 0;
+ if (simulate_inst_stalls && icache_access)
+ stall_ticks += icache_latency;
+
+ if (simulate_data_stalls && dcache_access)
+ stall_ticks += dcache_latency;
+
+ if (stall_ticks) {
+ Tick stall_cycles = stall_ticks / ticks(1);
+ Tick aligned_stall_ticks = ticks(stall_cycles);
+
+ if (aligned_stall_ticks < stall_ticks)
+ aligned_stall_ticks += 1;
+
+ latency += aligned_stall_ticks;
}
}
@@ -786,6 +792,10 @@ AtomicSimpleCPU::tick()
advancePC(fault);
}
+ // instruction takes at least one cycle
+ if (latency < ticks(1))
+ latency = ticks(1);
+
if (_status != Idle)
tickEvent.schedule(curTick + latency);
}
@@ -819,7 +829,8 @@ AtomicSimpleCPUParams::create()
params->functionTrace = function_trace;
params->functionTraceStart = function_trace_start;
params->width = width;
- params->simulate_stalls = simulate_stalls;
+ params->simulate_data_stalls = simulate_data_stalls;
+ params->simulate_inst_stalls = simulate_inst_stalls;
params->system = system;
params->cpu_id = cpu_id;
params->tracer = tracer;
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 19bc0e13b..ccea15073 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -39,7 +39,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
struct Params : public BaseSimpleCPU::Params {
int width;
- bool simulate_stalls;
+ bool simulate_data_stalls;
+ bool simulate_inst_stalls;
};
AtomicSimpleCPU(Params *params);
@@ -74,7 +75,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
TickEvent tickEvent;
const int width;
- const bool simulate_stalls;
+ const bool simulate_data_stalls;
+ const bool simulate_inst_stalls;
// main simulation loop (one cycle)
void tick();
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 93772fbe1..47b69d05f 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -86,11 +86,8 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
profileNode = &dummyNode;
profilePC = 3;
- if (use_kernel_stats) {
+ if (use_kernel_stats)
kernelStats = new TheISA::Kernel::Statistics(system);
- } else {
- kernelStats = NULL;
- }
}
#else
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process,
@@ -305,7 +302,6 @@ void
SimpleThread::delVirtPort(VirtualPort *vp)
{
if (vp != virtPort) {
- vp->removeConn();
delete vp;
}
}
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index be8f822f2..56839ca7f 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -46,7 +46,7 @@
ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid)
: baseCpu(cpu), cpuId(_cpuId), tid(_tid), lastActivate(0), lastSuspend(0),
profile(NULL), profileNode(NULL), profilePC(0), quiesceEvent(NULL),
- physPort(NULL), virtPort(NULL),
+ kernelStats(NULL), physPort(NULL), virtPort(NULL),
microPC(0), nextMicroPC(1), funcExeInst(0), storeCondFailures(0)
#else
ThreadState::ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
@@ -126,7 +126,7 @@ ThreadState::connectPhysPort()
// already existed. Fix this memory leak once the bus port IDs
// for functional ports is resolved.
if (physPort)
- physPort->removeConn();
+ physPort->disconnectFromPeer();
else
physPort = new FunctionalPort(csprintf("%s-%d-funcport",
baseCpu->name(), tid));
@@ -140,7 +140,7 @@ ThreadState::connectVirtPort()
// already existed. Fix this memory leak once the bus port IDs
// for functional ports is resolved.
if (virtPort)
- virtPort->removeConn();
+ virtPort->disconnectFromPeer();
else
virtPort = new VirtualPort(csprintf("%s-%d-vport",
baseCpu->name(), tid));
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-25 01:51:50 +0000