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-rw-r--r--src/cpu/o3/cpu.cc2
-rw-r--r--src/cpu/o3/dyn_inst.hh4
-rw-r--r--src/cpu/o3/fetch_impl.hh2
-rw-r--r--src/cpu/o3/inst_queue_impl.hh2
-rw-r--r--src/cpu/ozone/inst_queue_impl.hh2
-rw-r--r--src/cpu/pc_event.cc2
-rw-r--r--src/cpu/simple/base.cc2
-rw-r--r--src/cpu/static_inst.cc2
8 files changed, 12 insertions, 6 deletions
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 66c75a12d..785165636 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -45,7 +45,7 @@
#include "cpu/o3/isa_specific.hh"
#include "cpu/o3/cpu.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "sim/stat_control.hh"
#if USE_CHECKER
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 279513493..c37f8007e 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -45,6 +45,10 @@
template <class Impl> class SparcDynInst;
struct SparcSimpleImpl;
typedef SparcDynInst<SparcSimpleImpl> O3DynInst;
+#elif THE_ISA == X86_ISA
+ template <class Impl> class X86DynInst;
+ struct X86SimpleImpl;
+ typedef X86DynInst<X86SimpleImpl> O3DynInst;
#else
#error "O3DynInst not defined for this ISA"
#endif
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index e6a779823..ac0149d18 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -40,7 +40,7 @@
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/host.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
#if FULL_SYSTEM
#include "arch/tlb.hh"
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 98b8fa900..d5781d89d 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -32,7 +32,7 @@
#include <limits>
#include <vector>
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
diff --git a/src/cpu/ozone/inst_queue_impl.hh b/src/cpu/ozone/inst_queue_impl.hh
index 84f2b2a19..ea9d03c0d 100644
--- a/src/cpu/ozone/inst_queue_impl.hh
+++ b/src/cpu/ozone/inst_queue_impl.hh
@@ -38,7 +38,7 @@
#include <vector>
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "cpu/ozone/inst_queue.hh"
#if 0
diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc
index fca357fe3..7ab8bfcb8 100644
--- a/src/cpu/pc_event.cc
+++ b/src/cpu/pc_event.cc
@@ -40,7 +40,7 @@
#include "cpu/thread_context.hh"
#include "cpu/pc_event.hh"
#include "sim/debug.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
#include "sim/system.hh"
using namespace std;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 80b137909..f6c109127 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -371,6 +371,8 @@ BaseSimpleCPU::preExecute()
StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->readPC()));
#elif THE_ISA == SPARC_ISA
StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
+#elif THE_ISA == X86_ISA
+ StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
#elif THE_ISA == MIPS_ISA
//Mips doesn't do anything in it's MakeExtMI function right now,
//so it won't be called.
diff --git a/src/cpu/static_inst.cc b/src/cpu/static_inst.cc
index cb4a7cdf7..64fcc0580 100644
--- a/src/cpu/static_inst.cc
+++ b/src/cpu/static_inst.cc
@@ -31,7 +31,7 @@
#include <iostream>
#include "cpu/static_inst.hh"
-#include "sim/root.hh"
+#include "sim/core.hh"
StaticInstPtr StaticInst::nullStaticInstPtr;