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-rw-r--r--src/cpu/BaseCPU.py67
-rw-r--r--src/cpu/base.hh2
-rwxr-xr-xsrc/cpu/o3/thread_context.hh14
-rwxr-xr-xsrc/cpu/o3/thread_context_impl.hh42
-rw-r--r--src/cpu/simple/base.cc36
-rw-r--r--src/cpu/simple/base.hh2
-rw-r--r--src/cpu/static_inst.hh3
-rw-r--r--src/cpu/thread_context.hh24
8 files changed, 111 insertions, 79 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 9fc1db9f1..691f92e2e 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -44,7 +44,7 @@ elif build_env['TARGET_ISA'] == 'sparc':
elif build_env['TARGET_ISA'] == 'x86':
from X86TLB import X86DTB, X86ITB
elif build_env['TARGET_ISA'] == 'mips':
- from MipsTLB import MipsDTB, MipsITB
+ from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB
class BaseCPU(SimObject):
type = 'BaseCPU'
@@ -72,8 +72,10 @@ class BaseCPU(SimObject):
dtb = Param.X86DTB(X86DTB(), "Data TLB")
itb = Param.X86ITB(X86ITB(), "Instruction TLB")
elif build_env['TARGET_ISA'] == 'mips':
+ UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
itb = Param.MipsITB(MipsITB(), "Instruction TLB")
+ tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
else:
print "Don't know what TLB to use for ISA %s" % \
build_env['TARGET_ISA']
@@ -100,23 +102,18 @@ class BaseCPU(SimObject):
_mem_ports = []
- if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
- _mem_ports = ["itb.walker.port", "dtb.walker.port"]
-
def connectMemPorts(self, bus):
for p in self._mem_ports:
if p != 'physmem_port':
exec('self.%s = bus.port' % p)
def addPrivateSplitL1Caches(self, ic, dc):
- assert(len(self._mem_ports) < 6)
+ assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3)
self.icache = ic
self.dcache = dc
self.icache_port = ic.cpu_side
self.dcache_port = dc.cpu_side
self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
- if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
- self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
self.addPrivateSplitL1Caches(ic, dc)
@@ -125,3 +122,59 @@ class BaseCPU(SimObject):
self.l2cache = l2c
self.l2cache.cpu_side = self.toL2Bus.port
self._mem_ports = ['l2cache.mem_side']
+
+ if build_env['TARGET_ISA'] == 'mips':
+ CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description")
+ CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description")
+ CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description")
+ CP0_EBase_CPUNum = Param.Unsigned(0,"No Description")
+ CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register")
+ CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register")
+ CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company")
+ CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register")
+ CP0_Config_BE = Param.Unsigned(0,"Big Endian?")
+ CP0_Config_AT = Param.Unsigned(0,"No Description")
+ CP0_Config_AR = Param.Unsigned(0,"No Description")
+ CP0_Config_MT = Param.Unsigned(0,"No Description")
+ CP0_Config_VI = Param.Unsigned(0,"No Description")
+ CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?")
+ CP0_Config1_MMU = Param.Unsigned(0,"MMU Type")
+ CP0_Config1_IS = Param.Unsigned(0,"No Description")
+ CP0_Config1_IL = Param.Unsigned(0,"No Description")
+ CP0_Config1_IA = Param.Unsigned(0,"No Description")
+ CP0_Config1_DS = Param.Unsigned(0,"No Description")
+ CP0_Config1_DL = Param.Unsigned(0,"No Description")
+ CP0_Config1_DA = Param.Unsigned(0,"No Description")
+ CP0_Config1_C2 = Param.Bool(False,"No Description")
+ CP0_Config1_MD = Param.Bool(False,"No Description")
+ CP0_Config1_PC = Param.Bool(False,"No Description")
+ CP0_Config1_WR = Param.Bool(False,"No Description")
+ CP0_Config1_CA = Param.Bool(False,"No Description")
+ CP0_Config1_EP = Param.Bool(False,"No Description")
+ CP0_Config1_FP = Param.Bool(False,"FPU Implemented?")
+ CP0_Config2_M = Param.Bool(False,"Config3 Implemented?")
+ CP0_Config2_TU = Param.Unsigned(0,"No Description")
+ CP0_Config2_TS = Param.Unsigned(0,"No Description")
+ CP0_Config2_TL = Param.Unsigned(0,"No Description")
+ CP0_Config2_TA = Param.Unsigned(0,"No Description")
+ CP0_Config2_SU = Param.Unsigned(0,"No Description")
+ CP0_Config2_SS = Param.Unsigned(0,"No Description")
+ CP0_Config2_SL = Param.Unsigned(0,"No Description")
+ CP0_Config2_SA = Param.Unsigned(0,"No Description")
+ CP0_Config3_M = Param.Bool(False,"Config4 Implemented?")
+ CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?")
+ CP0_Config3_LPA = Param.Bool(False,"No Description")
+ CP0_Config3_VEIC = Param.Bool(False,"No Description")
+ CP0_Config3_VInt = Param.Bool(False,"No Description")
+ CP0_Config3_SP = Param.Bool(False,"No Description")
+ CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?")
+ CP0_Config3_SM = Param.Bool(False,"No Description")
+ CP0_Config3_TL = Param.Bool(False,"No Description")
+ CP0_WatchHi_M = Param.Bool(False,"No Description")
+ CP0_PerfCtr_M = Param.Bool(False,"No Description")
+ CP0_PerfCtr_W = Param.Bool(False,"No Description")
+ CP0_PRId = Param.Unsigned(0,"CP0 Status Register")
+ CP0_Config = Param.Unsigned(0,"CP0 Config Register")
+ CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register")
+ CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register")
+ CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register")
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 3c3e91523..e0d2340e9 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -189,6 +189,8 @@ class BaseCPU : public MemObject
Tick progress_interval;
BaseCPU *checker;
+ TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
+
Params();
};
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 55b385d11..44ff8da8a 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -117,13 +117,13 @@ class O3ThreadContext : public ThreadContext
virtual void activate(int delay = 1);
/** Set the status to Suspended. */
- virtual void suspend();
+ virtual void suspend(int delay = 0);
/** Set the status to Unallocated. */
virtual void deallocate(int delay = 0);
/** Set the status to Halted. */
- virtual void halt();
+ virtual void halt(int delay = 0);
#if FULL_SYSTEM
/** Dumps the function profiling information.
@@ -203,16 +203,6 @@ class O3ThreadContext : public ThreadContext
/** Sets this thread's next PC. */
virtual void setNextPC(uint64_t val);
- virtual uint64_t readMicroPC()
- { return cpu->readMicroPC(thread->readTid()); }
-
- virtual void setMicroPC(uint64_t val);
-
- virtual uint64_t readNextMicroPC()
- { return cpu->readNextMicroPC(thread->readTid()); }
-
- virtual void setNextMicroPC(uint64_t val);
-
/** Reads a miscellaneous register. */
virtual MiscReg readMiscRegNoEffect(int misc_reg)
{ return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); }
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 55584629e..2d329b056 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -136,7 +136,7 @@ O3ThreadContext<Impl>::activate(int delay)
template <class Impl>
void
-O3ThreadContext<Impl>::suspend()
+O3ThreadContext<Impl>::suspend(int delay)
{
DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
getThreadNum());
@@ -177,7 +177,7 @@ O3ThreadContext<Impl>::deallocate(int delay)
template <class Impl>
void
-O3ThreadContext<Impl>::halt()
+O3ThreadContext<Impl>::halt(int delay)
{
DPRINTF(O3CPU, "Calling halt on Thread Context %d\n",
getThreadNum());
@@ -289,13 +289,9 @@ O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
// Copy the misc regs.
TheISA::copyMiscRegs(tc, this);
- // Then finally set the PC, the next PC, the nextNPC, the micropc, and the
- // next micropc.
+ // Then finally set the PC and the next PC.
cpu->setPC(tc->readPC(), tid);
cpu->setNextPC(tc->readNextPC(), tid);
- cpu->setNextNPC(tc->readNextNPC(), tid);
- cpu->setMicroPC(tc->readMicroPC(), tid);
- cpu->setNextMicroPC(tc->readNextMicroPC(), tid);
#if !FULL_SYSTEM
this->thread->funcExeInst = tc->readFuncExeInst();
#endif
@@ -318,7 +314,6 @@ template <class Impl>
TheISA::FloatReg
O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
switch(width) {
case 32:
return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
@@ -334,7 +329,6 @@ template <class Impl>
TheISA::FloatReg
O3ThreadContext<Impl>::readFloatReg(int reg_idx)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
return cpu->readArchFloatRegSingle(reg_idx, thread->readTid());
}
@@ -343,7 +337,6 @@ TheISA::FloatRegBits
O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
{
DPRINTF(Fault, "Reading floatint register through the TC!\n");
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
}
@@ -351,7 +344,6 @@ template <class Impl>
TheISA::FloatRegBits
O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
return cpu->readArchFloatRegInt(reg_idx, thread->readTid());
}
@@ -372,7 +364,6 @@ template <class Impl>
void
O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
switch(width) {
case 32:
cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
@@ -392,7 +383,6 @@ template <class Impl>
void
O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid());
if (!thread->trapPending && !thread->inSyscall) {
@@ -406,7 +396,6 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
int width)
{
DPRINTF(Fault, "Setting floatint register through the TC!\n");
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
// Squash if we're not already in a state update mode.
@@ -419,7 +408,6 @@ template <class Impl>
void
O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
{
- reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
cpu->setArchFloatRegInt(reg_idx, val, thread->readTid());
// Squash if we're not already in a state update mode.
@@ -454,30 +442,6 @@ O3ThreadContext<Impl>::setNextPC(uint64_t val)
template <class Impl>
void
-O3ThreadContext<Impl>::setMicroPC(uint64_t val)
-{
- cpu->setMicroPC(val, thread->readTid());
-
- // Squash if we're not already in a state update mode.
- if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromTC(thread->readTid());
- }
-}
-
-template <class Impl>
-void
-O3ThreadContext<Impl>::setNextMicroPC(uint64_t val)
-{
- cpu->setNextMicroPC(val, thread->readTid());
-
- // Squash if we're not already in a state update mode.
- if (!thread->trapPending && !thread->inSyscall) {
- cpu->squashFromTC(thread->readTid());
- }
-}
-
-template <class Impl>
-void
O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
{
cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid());
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 98e29d8d1..010c21e4a 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -466,9 +466,9 @@ BaseSimpleCPU::advancePC(Fault fault)
if (fault != NoFault) {
curMacroStaticInst = StaticInst::nullStaticInstPtr;
predecoder.reset();
+ fault->invoke(tc);
thread->setMicroPC(0);
thread->setNextMicroPC(1);
- fault->invoke(tc);
} else {
//If we're at the last micro op for this instruction
if (curStaticInst && curStaticInst->isLastMicroop()) {
@@ -503,3 +503,37 @@ BaseSimpleCPU::advancePC(Fault fault)
} while (oldpc != thread->readPC());
}
+/*Fault
+BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
+{
+ // translate to physical address
+ Fault fault = NoFault;
+ int CacheID = Op & 0x3; // Lower 3 bits identify Cache
+ int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
+ if(CacheID > 1)
+ {
+ warn("CacheOps not implemented for secondary/tertiary caches\n");
+ }
+ else
+ {
+ switch(CacheOP)
+ { // Fill Packet Type
+ case 0: warn("Invalidate Cache Op\n");
+ break;
+ case 1: warn("Index Load Tag Cache Op\n");
+ break;
+ case 2: warn("Index Store Tag Cache Op\n");
+ break;
+ case 4: warn("Hit Invalidate Cache Op\n");
+ break;
+ case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
+ break;
+ case 6: warn("Hit Writeback\n");
+ break;
+ case 7: warn("Fetch & Lock Cache Op\n");
+ break;
+ default: warn("Unimplemented Cache Op\n");
+ }
+ }
+ return fault;
+}*/
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 337ef5285..82f73e5dd 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -378,6 +378,8 @@ class BaseSimpleCPU : public BaseCPU
"register access.\n");
}
+ //Fault CacheOp(uint8_t Op, Addr EA);
+
#if FULL_SYSTEM
Fault hwrei() { return thread->hwrei(); }
void ev5_trap(Fault fault) { fault->invoke(tc); }
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index c02c1c3bc..d2232bab7 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -114,6 +114,7 @@ class StaticInstBase : public RefCounted
IsLoad, ///< Reads from memory (load or prefetch).
IsStore, ///< Writes to memory.
IsStoreConditional, ///< Store conditional instruction.
+ IsIndexed, ///< Accesses memory with an indexed address computation
IsInstPrefetch, ///< Instruction-cache prefetch.
IsDataPrefetch, ///< Data-cache prefetch.
IsCopy, ///< Fast Cache block copy
@@ -136,6 +137,7 @@ class StaticInstBase : public RefCounted
IsSerializeAfter,
IsMemBarrier, ///< Is a memory barrier
IsWriteBarrier, ///< Is a write barrier
+ IsERET, /// <- Causes the IFU to stall (MIPS ISA)
IsNonSpeculative, ///< Should not be executed speculatively
IsQuiesce, ///< Is a quiesce instruction
@@ -154,6 +156,7 @@ class StaticInstBase : public RefCounted
IsFirstMicroop, ///< This microop begins a microop sequence
//This flag doesn't do anything yet
IsMicroBranch, ///< This microop branches within the microcode for a macroop
+ IsDspOp,
NumFlags
};
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 0d09492ee..9f6af8890 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -150,13 +150,13 @@ class ThreadContext
virtual void activate(int delay = 1) = 0;
/// Set the status to Suspended.
- virtual void suspend() = 0;
+ virtual void suspend(int delay = 0) = 0;
/// Set the status to Unallocated.
virtual void deallocate(int delay = 0) = 0;
/// Set the status to Halted.
- virtual void halt() = 0;
+ virtual void halt(int delay = 0) = 0;
#if FULL_SYSTEM
virtual void dumpFuncProfile() = 0;
@@ -226,14 +226,6 @@ class ThreadContext
virtual void setNextNPC(uint64_t val) = 0;
- virtual uint64_t readMicroPC() = 0;
-
- virtual void setMicroPC(uint64_t val) = 0;
-
- virtual uint64_t readNextMicroPC() = 0;
-
- virtual void setNextMicroPC(uint64_t val) = 0;
-
virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
virtual MiscReg readMiscReg(int misc_reg) = 0;
@@ -341,13 +333,13 @@ class ProxyThreadContext : public ThreadContext
void activate(int delay = 1) { actualTC->activate(delay); }
/// Set the status to Suspended.
- void suspend() { actualTC->suspend(); }
+ void suspend(int delay = 0) { actualTC->suspend(); }
/// Set the status to Unallocated.
void deallocate(int delay = 0) { actualTC->deallocate(); }
/// Set the status to Halted.
- void halt() { actualTC->halt(); }
+ void halt(int delay = 0) { actualTC->halt(); }
#if FULL_SYSTEM
void dumpFuncProfile() { actualTC->dumpFuncProfile(); }
@@ -427,14 +419,6 @@ class ProxyThreadContext : public ThreadContext
void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); }
- uint64_t readMicroPC() { return actualTC->readMicroPC(); }
-
- void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); }
-
- uint64_t readNextMicroPC() { return actualTC->readMicroPC(); }
-
- void setNextMicroPC(uint64_t val) { actualTC->setMicroPC(val); }
-
MiscReg readMiscRegNoEffect(int misc_reg)
{ return actualTC->readMiscRegNoEffect(misc_reg); }
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-23 18:23:51 +0000