5 files changed, 60 insertions, 0 deletions

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 759bc0881..4fc2ebf1b 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -100,6 +100,25 @@ class BaseCPU(MemObject):
     void flushTLBs();
 ''')
 
+    @classmethod
+    def memory_mode(cls):
+        """Which memory mode does this CPU require?"""
+        return 'invalid'
+
+    @classmethod
+    def require_caches(cls):
+        """Does the CPU model require caches?
+
+        Some CPU models might make assumptions that require them to
+        have caches.
+        """
+        return False
+
+    @classmethod
+    def support_take_over(cls):
+        """Does the CPU model support CPU takeOverFrom?"""
+        return False
+
     def takeOverFrom(self, old_cpu):
         self._ccObject.takeOverFrom(old_cpu._ccObject)
 
diff --git a/src/cpu/inorder/InOrderCPU.py b/src/cpu/inorder/InOrderCPU.py
index 3285d50ce..e29a29556 100644
--- a/src/cpu/inorder/InOrderCPU.py
+++ b/src/cpu/inorder/InOrderCPU.py
@@ -39,6 +39,14 @@ class InOrderCPU(BaseCPU):
     cxx_header = "cpu/inorder/cpu.hh"
     activity = Param.Unsigned(0, "Initial count")
 
+    @classmethod
+    def memory_mode(cls):
+        return 'timing'
+
+    @classmethod
+    def require_caches(cls):
+        return True
+
     threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
     
     cachePorts = Param.Unsigned(2, "Cache Ports")
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index 4f720a8f6..f46388b4c 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -38,6 +38,18 @@ class DerivO3CPU(BaseCPU):
     type = 'DerivO3CPU'
     cxx_header = 'cpu/o3/deriv.hh'
 
+    @classmethod
+    def memory_mode(cls):
+        return 'timing'
+
+    @classmethod
+    def require_caches(cls):
+        return True
+
+    @classmethod
+    def support_take_over(cls):
+        return True
+
     activity = Param.Unsigned(0, "Initial count")
 
     cachePorts = Param.Unsigned(200, "Cache Ports")
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 1927a5862..c747582f6 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -42,8 +42,21 @@ from m5.params import *
 from BaseSimpleCPU import BaseSimpleCPU
 
 class AtomicSimpleCPU(BaseSimpleCPU):
+    """Simple CPU model executing a configurable number of
+    instructions per cycle. This model uses the simplified 'atomic'
+    memory mode."""
+
     type = 'AtomicSimpleCPU'
     cxx_header = "cpu/simple/atomic.hh"
+
+    @classmethod
+    def memory_mode(cls):
+        return 'atomic'
+
+    @classmethod
+    def support_take_over(cls):
+        return True
+
     width = Param.Int(1, "CPU width")
     simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
     simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index 72560366e..25149eaa8 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -32,3 +32,11 @@ from BaseSimpleCPU import BaseSimpleCPU
 class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'
     cxx_header = "cpu/simple/timing.hh"
+
+    @classmethod
+    def memory_mode(cls):
+        return 'timing'
+
+    @classmethod
+    def support_take_over(cls):
+        return True