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-rw-r--r--src/cpu/base_dyn_inst.hh63
-rw-r--r--src/cpu/exec_context.hh17
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.cc144
-rw-r--r--src/cpu/inorder/inorder_dyn_inst.hh29
-rw-r--r--src/cpu/simple/atomic.cc148
-rw-r--r--src/cpu/simple/atomic.hh12
-rw-r--r--src/cpu/simple/timing.cc149
-rw-r--r--src/cpu/simple/timing.hh17
8 files changed, 37 insertions, 542 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 4c7abe376..f0d36cc83 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -124,31 +124,10 @@ class BaseDynInst : public FastAlloc, public RefCounted
cpu->demapPage(vaddr, asn);
}
- /**
- * Does a read to a given address.
- * @param addr The address to read.
- * @param data The read's data is written into this parameter.
- * @param flags The request's flags.
- * @return Returns any fault due to the read.
- */
- template <class T>
- Fault read(Addr addr, T &data, unsigned flags);
-
- Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
- /**
- * Does a write to a given address.
- * @param data The data to be written.
- * @param addr The address to write to.
- * @param flags The request's flags.
- * @param res The result of the write (for load locked/store conditionals).
- * @return Returns any fault due to the write.
- */
- template <class T>
- Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
- Fault writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Fault writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res);
/** Splits a request in two if it crosses a dcache block. */
void splitRequest(RequestPtr req, RequestPtr &sreqLow,
@@ -862,8 +841,8 @@ class BaseDynInst : public FastAlloc, public RefCounted
template<class Impl>
Fault
-BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
- unsigned size, unsigned flags)
+BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data,
+ unsigned size, unsigned flags)
{
reqMade = true;
Request *req = NULL;
@@ -913,25 +892,9 @@ BaseDynInst<Impl>::readBytes(Addr addr, uint8_t *data,
}
template<class Impl>
-template<class T>
-inline Fault
-BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
-{
- Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
-
- data = TheISA::gtoh(data);
-
- if (traceData) {
- traceData->setData(data);
- }
-
- return fault;
-}
-
-template<class Impl>
Fault
-BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res)
+BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res)
{
if (traceData) {
traceData->setAddr(addr);
@@ -968,18 +931,6 @@ BaseDynInst<Impl>::writeBytes(uint8_t *data, unsigned size,
}
template<class Impl>
-template<class T>
-inline Fault
-BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
-{
- if (traceData) {
- traceData->setData(data);
- }
- data = TheISA::htog(data);
- return writeBytes((uint8_t *)&data, sizeof(T), addr, flags, res);
-}
-
-template<class Impl>
inline void
BaseDynInst<Impl>::splitRequest(RequestPtr req, RequestPtr &sreqLow,
RequestPtr &sreqHigh)
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index a8704851f..61c9b24a9 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -106,21 +106,10 @@ class ExecContext {
/** Returns a pointer to the ThreadContext. */
ThreadContext *tcBase();
- /** Reads an address, creating a memory request with the given
- * flags. Stores result of read in data. */
- template <class T>
- Fault read(Addr addr, T &data, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
- Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
- /** Writes to an address, creating a memory request with the given
- * flags. Writes data to memory. For store conditionals, returns
- * the result of the store in res. */
- template <class T>
- Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
-
- Fault writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Fault writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res);
#if FULL_SYSTEM
/** Somewhat Alpha-specific function that handles returning from
diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index a90c2cdb4..5343206c1 100644
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -559,155 +559,19 @@ InOrderDynInst::deallocateContext(int thread_num)
}
Fault
-InOrderDynInst::readBytes(Addr addr, uint8_t *data,
- unsigned size, unsigned flags)
+InOrderDynInst::readMem(Addr addr, uint8_t *data,
+ unsigned size, unsigned flags)
{
return cpu->read(this, addr, data, size, flags);
}
-template<class T>
-inline Fault
-InOrderDynInst::read(Addr addr, T &data, unsigned flags)
-{
- if (traceData) {
- traceData->setAddr(addr);
- traceData->setData(data);
- }
- Fault fault = readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
- //@todo: the below lines should be unnecessary, timing access
- // wont have valid data right here
- DPRINTF(InOrderDynInst, "[sn:%i] (1) Received Bytes %x\n", seqNum, data);
- data = TheISA::gtoh(data);
- DPRINTF(InOrderDynInst, "[sn%:i] (2) Received Bytes %x\n", seqNum, data);
-
- if (traceData)
- traceData->setData(data);
- return fault;
-}
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-InOrderDynInst::read(Addr addr, Twin32_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, Twin64_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, uint64_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, uint32_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, uint16_t &data, unsigned flags);
-
-template
-Fault
-InOrderDynInst::read(Addr addr, uint8_t &data, unsigned flags);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-InOrderDynInst::read(Addr addr, double &data, unsigned flags)
-{
- return read(addr, *(uint64_t*)&data, flags);
-}
-
-template<>
-Fault
-InOrderDynInst::read(Addr addr, float &data, unsigned flags)
-{
- return read(addr, *(uint32_t*)&data, flags);
-}
-
-template<>
-Fault
-InOrderDynInst::read(Addr addr, int32_t &data, unsigned flags)
-{
- return read(addr, (uint32_t&)data, flags);
-}
-
Fault
-InOrderDynInst::writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res)
+InOrderDynInst::writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res)
{
return cpu->write(this, data, size, addr, flags, res);
}
-template<class T>
-inline Fault
-InOrderDynInst::write(T data, Addr addr, unsigned flags, uint64_t *res)
-{
- if (traceData) {
- traceData->setAddr(addr);
- traceData->setData(data);
- }
- data = TheISA::htog(data);
- return writeBytes((uint8_t*)&data, sizeof(T), addr, flags, res);
-}
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-InOrderDynInst::write(Twin32_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-InOrderDynInst::write(Twin64_t data, Addr addr,
- unsigned flags, uint64_t *res);
-template
-Fault
-InOrderDynInst::write(uint64_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-InOrderDynInst::write(uint32_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-InOrderDynInst::write(uint16_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-InOrderDynInst::write(uint8_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-InOrderDynInst::write(double data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write(*(uint64_t*)&data, addr, flags, res);
-}
-
-template<>
-Fault
-InOrderDynInst::write(float data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write(*(uint32_t*)&data, addr, flags, res);
-}
-
-
-template<>
-Fault
-InOrderDynInst::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write((uint32_t)data, addr, flags, res);
-}
-
void
InOrderDynInst::dump()
diff --git a/src/cpu/inorder/inorder_dyn_inst.hh b/src/cpu/inorder/inorder_dyn_inst.hh
index 205bb0f82..ecaf23aab 100644
--- a/src/cpu/inorder/inorder_dyn_inst.hh
+++ b/src/cpu/inorder/inorder_dyn_inst.hh
@@ -612,32 +612,11 @@ class InOrderDynInst : public FastAlloc, public RefCounted
// MEMORY ACCESS
//
////////////////////////////////////////////
- /**
- * Does a read to a given address.
- * @param addr The address to read.
- * @param data The read's data is written into this parameter.
- * @param flags The request's flags.
- * @return Returns any fault due to the read.
- */
- template <class T>
- Fault read(Addr addr, T &data, unsigned flags);
-
- Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
- /**
- * Does a write to a given address.
- * @param data The data to be written.
- * @param addr The address to write to.
- * @param flags The request's flags.
- * @param res The result of the write (for load locked/store conditionals).
- * @return Returns any fault due to the write.
- */
- template <class T>
- Fault write(T data, Addr addr, unsigned flags,
- uint64_t *res);
- Fault writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
+
+ Fault writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res);
/** Initiates a memory access - Calculate Eff. Addr & Initiate Memory
* Access Only valid for memory operations.
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index f3d79dd2b..5376519d4 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -299,8 +299,8 @@ AtomicSimpleCPU::suspendContext(int thread_num)
Fault
-AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
- unsigned size, unsigned flags)
+AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
+ unsigned size, unsigned flags)
{
// use the CPU's statically allocated read request and packet objects
Request *req = &data_read_req;
@@ -386,75 +386,9 @@ AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
}
-template <class T>
Fault
-AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
-{
- uint8_t *dataPtr = (uint8_t *)&data;
- memset(dataPtr, 0, sizeof(data));
- Fault fault = readBytes(addr, dataPtr, sizeof(data), flags);
- if (fault == NoFault) {
- data = gtoh(data);
- if (traceData)
- traceData->setData(data);
- }
- return fault;
-}
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
-
-template
-Fault
-AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
-{
- return read(addr, *(uint64_t*)&data, flags);
-}
-
-template<>
-Fault
-AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
-{
- return read(addr, *(uint32_t*)&data, flags);
-}
-
-
-template<>
-Fault
-AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
-{
- return read(addr, (uint32_t&)data, flags);
-}
-
-
-Fault
-AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res)
+AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res)
{
// use the CPU's statically allocated write request and packet objects
Request *req = &data_write_req;
@@ -555,80 +489,6 @@ AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size,
}
-template <class T>
-Fault
-AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
-{
- uint8_t *dataPtr = (uint8_t *)&data;
- if (traceData)
- traceData->setData(data);
- data = htog(data);
-
- Fault fault = writeBytes(dataPtr, sizeof(data), addr, flags, res);
- if (fault == NoFault && data_write_req.isSwap()) {
- *res = gtoh((T)*res);
- }
- return fault;
-}
-
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-AtomicSimpleCPU::write(Twin32_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(Twin64_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(uint64_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(uint32_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(uint16_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-AtomicSimpleCPU::write(uint8_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write(*(uint64_t*)&data, addr, flags, res);
-}
-
-template<>
-Fault
-AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write(*(uint32_t*)&data, addr, flags, res);
-}
-
-
-template<>
-Fault
-AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write((uint32_t)data, addr, flags, res);
-}
-
-
void
AtomicSimpleCPU::tick()
{
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 5ec1970e7..246afa0b2 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -131,16 +131,10 @@ class AtomicSimpleCPU : public BaseSimpleCPU
virtual void activateContext(int thread_num, int delay);
virtual void suspendContext(int thread_num);
- template <class T>
- Fault read(Addr addr, T &data, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
- Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
- template <class T>
- Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
-
- Fault writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Fault writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res);
/**
* Print state of address in memory system via PrintReq (for
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 187b38b85..1c726ba57 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -432,8 +432,8 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
}
Fault
-TimingSimpleCPU::readBytes(Addr addr, uint8_t *data,
- unsigned size, unsigned flags)
+TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
+ unsigned size, unsigned flags)
{
Fault fault;
const int asid = 0;
@@ -479,62 +479,6 @@ TimingSimpleCPU::readBytes(Addr addr, uint8_t *data,
return NoFault;
}
-template <class T>
-Fault
-TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
-{
- return readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
-}
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
-
-template
-Fault
-TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
-{
- return read(addr, *(uint64_t*)&data, flags);
-}
-
-template<>
-Fault
-TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
-{
- return read(addr, *(uint32_t*)&data, flags);
-}
-
-template<>
-Fault
-TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
-{
- return read(addr, (uint32_t&)data, flags);
-}
-
bool
TimingSimpleCPU::handleWritePacket()
{
@@ -556,9 +500,12 @@ TimingSimpleCPU::handleWritePacket()
}
Fault
-TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res)
+TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res)
{
+ uint8_t *newData = new uint8_t[size];
+ memcpy(newData, data, size);
+
const int asid = 0;
const ThreadID tid = 0;
const Addr pc = thread->instAddr();
@@ -582,7 +529,7 @@ TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
req->splitOnVaddr(split_addr, req1, req2);
WholeTranslationState *state =
- new WholeTranslationState(req, req1, req2, data, res, mode);
+ new WholeTranslationState(req, req1, req2, newData, res, mode);
DataTranslation<TimingSimpleCPU> *trans1 =
new DataTranslation<TimingSimpleCPU>(this, state, 0);
DataTranslation<TimingSimpleCPU> *trans2 =
@@ -592,7 +539,7 @@ TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
thread->dtb->translateTiming(req2, tc, trans2, mode);
} else {
WholeTranslationState *state =
- new WholeTranslationState(req, data, res, mode);
+ new WholeTranslationState(req, newData, res, mode);
DataTranslation<TimingSimpleCPU> *translation =
new DataTranslation<TimingSimpleCPU>(this, state);
thread->dtb->translateTiming(req, tc, translation, mode);
@@ -602,84 +549,6 @@ TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
return NoFault;
}
-Fault
-TimingSimpleCPU::writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res)
-{
- uint8_t *newData = new uint8_t[size];
- memcpy(newData, data, size);
- return writeTheseBytes(newData, size, addr, flags, res);
-}
-
-template <class T>
-Fault
-TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
-{
- if (traceData) {
- traceData->setData(data);
- }
- T *dataP = (T*) new uint8_t[sizeof(T)];
- *dataP = TheISA::htog(data);
-
- return writeTheseBytes((uint8_t *)dataP, sizeof(T), addr, flags, res);
-}
-
-
-#ifndef DOXYGEN_SHOULD_SKIP_THIS
-template
-Fault
-TimingSimpleCPU::write(Twin32_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(Twin64_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint64_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint32_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint16_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-template
-Fault
-TimingSimpleCPU::write(uint8_t data, Addr addr,
- unsigned flags, uint64_t *res);
-
-#endif //DOXYGEN_SHOULD_SKIP_THIS
-
-template<>
-Fault
-TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write(*(uint64_t*)&data, addr, flags, res);
-}
-
-template<>
-Fault
-TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write(*(uint32_t*)&data, addr, flags, res);
-}
-
-
-template<>
-Fault
-TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
-{
- return write((uint32_t)data, addr, flags, res);
-}
-
void
TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 778506703..4301dfca7 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -256,16 +256,10 @@ class TimingSimpleCPU : public BaseSimpleCPU
virtual void activateContext(int thread_num, int delay);
virtual void suspendContext(int thread_num);
- template <class T>
- Fault read(Addr addr, T &data, unsigned flags);
+ Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
- Fault readBytes(Addr addr, uint8_t *data, unsigned size, unsigned flags);
-
- template <class T>
- Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
-
- Fault writeBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
+ Fault writeMem(uint8_t *data, unsigned size,
+ Addr addr, unsigned flags, uint64_t *res);
void fetch();
void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
@@ -287,11 +281,6 @@ class TimingSimpleCPU : public BaseSimpleCPU
private:
- // The backend for writeBytes and write. It's the same as writeBytes, but
- // doesn't make a copy of data.
- Fault writeTheseBytes(uint8_t *data, unsigned size,
- Addr addr, unsigned flags, uint64_t *res);
-
typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
FetchEvent fetchEvent;
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-23 17:29:14 +0000