4 files changed, 7 insertions, 14 deletions

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index c6e57b612..f4ff88209 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -857,9 +857,8 @@ inline Fault
 BaseDynInst<Impl>::read(Addr addr, T &data, unsigned flags)
 {
     reqMade = true;
-    Request *req = new Request();
-    req->setVirt(asid, addr, sizeof(T), flags, this->PC);
-    req->setThreadContext(thread->contextId(), threadNumber);
+    Request *req = new Request(asid, addr, sizeof(T), flags, this->PC,
+                               thread->contextId(), threadNumber);
 
     fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Read);
 
@@ -913,9 +912,8 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
     }
 
     reqMade = true;
-    Request *req = new Request();
-    req->setVirt(asid, addr, sizeof(T), flags, this->PC);
-    req->setThreadContext(thread->contextId(), threadNumber);
+    Request *req = new Request(asid, addr, sizeof(T), flags, this->PC,
+                               thread->contextId(), threadNumber);
 
     fault = cpu->dtb->translateAtomic(req, thread->getTC(), BaseTLB::Write);
 
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index a76e07576..3781113bd 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -596,9 +596,9 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, ThreadID tid
     // Setup the memReq to do a read of the first instruction's address.
     // Set the appropriate read size and flags as well.
     // Build request here.
-    RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
-                                     fetch_PC, cpu->thread[tid]->contextId(),
-                                     tid);
+    RequestPtr mem_req =
+        new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
+                    fetch_PC, cpu->thread[tid]->contextId(), tid);
 
     memReq[tid] = mem_req;
 
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index dd9e23f97..f242645a2 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -211,7 +211,6 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
         memReq->cmd = Read;
         memReq->completionEvent = NULL;
         memReq->time = curTick;
-        memReq->flags &= ~INST_FETCH;
         MemAccessResult result = dcacheInterface->access(memReq);
 
         // Ugly hack to get an event scheduled *only* if the access is
@@ -252,7 +251,6 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
 //      memcpy(memReq->data,(uint8_t *)&data,memReq->size);
         memReq->completionEvent = NULL;
         memReq->time = curTick;
-        memReq->flags &= ~INST_FETCH;
         MemAccessResult result = dcacheInterface->access(memReq);
 
         // Ugly hack to get an event scheduled *only* if the access is
@@ -293,7 +291,6 @@ InorderBackEnd<Impl>::read(MemReqPtr &req, T &data, int load_idx)
     req->time = curTick;
     assert(!req->data);
     req->data = new uint8_t[64];
-    req->flags &= ~INST_FETCH;
     Fault fault = cpu->read(req, data);
     memcpy(req->data, &data, sizeof(T));
 
@@ -363,7 +360,6 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
         memcpy(req->data,(uint8_t *)&data,req->size);
         req->completionEvent = NULL;
         req->time = curTick;
-        req->flags &= ~INST_FETCH;
         MemAccessResult result = dcacheInterface->access(req);
 
         // Ugly hack to get an event scheduled *only* if the access is
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 921c8c19d..732bb637b 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -282,7 +282,6 @@ BaseSimpleCPU::copy(Addr dest)
             memReq->dest = dest_addr;
             memReq->size = 64;
             memReq->time = curTick;
-            memReq->flags &= ~INST_FETCH;
             dcacheInterface->access(memReq);
         }
     }