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-rw-r--r--src/cpu/base_dyn_inst.hh12
-rw-r--r--src/cpu/checker/cpu.hh25
-rw-r--r--src/cpu/exec_context.hh25
-rw-r--r--src/cpu/o3/alpha/dyn_inst.hh35
-rwxr-xr-xsrc/cpu/o3/mips/dyn_inst.hh35
-rw-r--r--src/cpu/ozone/cpu.hh99
-rw-r--r--src/cpu/ozone/dyn_inst.hh25
-rw-r--r--src/cpu/ozone/inorder_back_end.hh74
-rw-r--r--src/cpu/simple/base.hh25
-rw-r--r--src/cpu/simple_thread.hh69
10 files changed, 101 insertions, 323 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 4a4555566..9037c96df 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -406,14 +406,15 @@ class BaseDynInst : public FastAlloc, public RefCounted
double readDoubleResult() { return instResult.dbl; }
/** Records an integer register being set to a value. */
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
if (recordResult)
instResult.integer = val;
}
/** Records an fp register being set to a value. */
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
if (recordResult) {
if (width == 32)
@@ -426,21 +427,22 @@ class BaseDynInst : public FastAlloc, public RefCounted
}
/** Records an fp register being set to a value. */
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
if (recordResult)
instResult.dbl = (double)val;
}
/** Records an fp register being set to an integer value. */
- void setFloatRegBits(const StaticInst *si, int idx, uint64_t val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val,
+ int width)
{
if (recordResult)
instResult.integer = val;
}
/** Records an fp register being set to an integer value. */
- void setFloatRegBits(const StaticInst *si, int idx, uint64_t val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx, uint64_t val)
{
if (recordResult)
instResult.integer = val;
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 9be54529f..3e08193ee 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -216,42 +216,44 @@ class CheckerCPU : public BaseCPU
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return thread->readIntReg(si->srcRegIdx(idx));
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatReg(reg_idx, width);
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatReg(reg_idx);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatRegBits(reg_idx, width);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatRegBits(reg_idx);
}
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
thread->setIntReg(si->destRegIdx(idx), val);
result.integer = val;
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatReg(reg_idx, val, width);
@@ -265,22 +267,23 @@ class CheckerCPU : public BaseCPU
};
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatReg(reg_idx, val);
result.dbl = (double)val;
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val,
- int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatRegBits(reg_idx, val, width);
result.integer = val;
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatRegBits(reg_idx, val);
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index 13f70fa79..edccd747f 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -48,39 +48,42 @@ class ExecContext {
// to do).
/** Reads an integer register. */
- uint64_t readIntReg(const StaticInst *si, int idx);
+ uint64_t readIntRegOperand(const StaticInst *si, int idx);
/** Reads a floating point register of a specific width. */
- FloatReg readFloatReg(const StaticInst *si, int idx, int width);
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width);
/** Reads a floating point register of single register width. */
- FloatReg readFloatReg(const StaticInst *si, int idx);
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx);
/** Reads a floating point register of a specific width in its
* binary format, instead of by value. */
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width);
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width);
/** Reads a floating point register in its binary format, instead
* of by value. */
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx);
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx);
/** Sets an integer register to a value. */
- void setIntReg(const StaticInst *si, int idx, uint64_t val);
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val);
/** Sets a floating point register of a specific width to a value. */
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width);
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width);
/** Sets a floating point register of single width to a value. */
- void setFloatReg(const StaticInst *si, int idx, FloatReg val);
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val);
/** Sets the bits of a floating point register of a specific width
* to a binary value. */
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width);
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width);
/** Sets the bits of a floating point register of single width
* to a binary value. */
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val);
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val);
/** Reads the PC. */
uint64_t readPC();
diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh
index 31df8ff78..49cc5a201 100644
--- a/src/cpu/o3/alpha/dyn_inst.hh
+++ b/src/cpu/o3/alpha/dyn_inst.hh
@@ -163,27 +163,28 @@ class AlphaDynInst : public BaseDynInst<Impl>
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readIntReg(_srcRegIdx[idx]);
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
return this->cpu->readFloatReg(_srcRegIdx[idx], width);
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readFloatReg(_srcRegIdx[idx]);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
return this->cpu->readFloatRegBits(_srcRegIdx[idx], width);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(_srcRegIdx[idx]);
}
@@ -191,35 +192,37 @@ class AlphaDynInst : public BaseDynInst<Impl>
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setIntReg(_destRegIdx[idx], val);
- BaseDynInst<Impl>::setIntReg(si, idx, val);
+ BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
this->cpu->setFloatReg(_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
this->cpu->setFloatReg(_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatReg(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
/** Returns the physical register index of the i'th destination
diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh
index 9e95b2bfb..833371e00 100755
--- a/src/cpu/o3/mips/dyn_inst.hh
+++ b/src/cpu/o3/mips/dyn_inst.hh
@@ -156,27 +156,28 @@ class MipsDynInst : public BaseDynInst<Impl>
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readIntReg(_srcRegIdx[idx]);
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
return this->cpu->readFloatReg(_srcRegIdx[idx], width);
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
return this->cpu->readFloatReg(_srcRegIdx[idx]);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
return this->cpu->readFloatRegBits(_srcRegIdx[idx], width);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(_srcRegIdx[idx]);
}
@@ -184,35 +185,37 @@ class MipsDynInst : public BaseDynInst<Impl>
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
this->cpu->setIntReg(_destRegIdx[idx], val);
- BaseDynInst<Impl>::setIntReg(si, idx, val);
+ BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
this->cpu->setFloatReg(_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val, width);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
this->cpu->setFloatReg(_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatReg(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
this->cpu->setFloatRegBits(_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
+ BaseDynInst<Impl>::setFloatRegOperandBits(si, idx, val);
}
/** Returns the physical register index of the i'th destination
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index c1373944d..0da446c9c 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -448,30 +448,6 @@ class OzoneCPU : public BaseCPU
}
#endif
- /** Old CPU read from memory function. No longer used. */
- template <class T>
- Fault read(Request *req, T &data)
- {
-#if 0
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- if (req->isLocked()) {
- req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
- req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
- }
-#endif
- if (req->isLocked()) {
- lockAddrList.insert(req->paddr);
- lockFlag = true;
- }
-#endif
- Fault error;
-
- error = this->mem->read(req, data);
- data = gtoh(data);
- return error;
- }
-
-
/** CPU read function, forwards read to LSQ. */
template <class T>
Fault read(Request *req, T &data, int load_idx)
@@ -479,81 +455,6 @@ class OzoneCPU : public BaseCPU
return backEnd->read(req, data, load_idx);
}
- /** Old CPU write to memory function. No longer used. */
- template <class T>
- Fault write(Request *req, T &data)
- {
-#if 0
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- ExecContext *xc;
-
- // If this is a store conditional, act appropriately
- if (req->isLocked()) {
- xc = req->xc;
-
- if (req->isUncacheable()) {
- // Don't update result register (see stq_c in isa_desc)
- req->result = 2;
- xc->setStCondFailures(0);//Needed? [RGD]
- } else {
- bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
- Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
- req->result = lock_flag;
- if (!lock_flag ||
- ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- xc->setStCondFailures(xc->readStCondFailures() + 1);
- if (((xc->readStCondFailures()) % 100000) == 0) {
- std::cerr << "Warning: "
- << xc->readStCondFailures()
- << " consecutive store conditional failures "
- << "on cpu " << req->xc->readCpuId()
- << std::endl;
- }
- return NoFault;
- }
- else xc->setStCondFailures(0);
- }
- }
-
- // Need to clear any locked flags on other proccessors for
- // this address. Only do this for succsful Store Conditionals
- // and all other stores (WH64?). Unsuccessful Store
- // Conditionals would have returned above, and wouldn't fall
- // through.
- for (int i = 0; i < this->system->threadContexts.size(); i++){
- xc = this->system->threadContexts[i];
- if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
- (req->paddr & ~0xf)) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- }
- }
-
-#endif
-
- if (req->isLocked()) {
- if (req->isUncacheable()) {
- req->result = 2;
- } else {
- if (this->lockFlag) {
- if (lockAddrList.find(req->paddr) !=
- lockAddrList.end()) {
- req->result = 1;
- } else {
- req->result = 0;
- return NoFault;
- }
- } else {
- req->result = 0;
- return NoFault;
- }
- }
- }
-#endif
-
- return this->mem->write(req, (T)htog(data));
- }
-
/** CPU write function, forwards write to LSQ. */
template <class T>
Fault write(Request *req, T &data, int store_idx)
diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index 9445a5309..88f96b14b 100644
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -146,12 +146,12 @@ class OzoneDynInst : public BaseDynInst<Impl>
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return srcInsts[idx]->readIntResult();
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
switch(width) {
case 32:
@@ -164,17 +164,18 @@ class OzoneDynInst : public BaseDynInst<Impl>
}
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
return srcInsts[idx]->readFloatResult();
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
return srcInsts[idx]->readIntResult();
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
return srcInsts[idx]->readIntResult();
}
@@ -182,28 +183,30 @@ class OzoneDynInst : public BaseDynInst<Impl>
/** @todo: Make results into arrays so they can handle multiple dest
* registers.
*/
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
BaseDynInst<Impl>::setIntReg(si, idx, val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
BaseDynInst<Impl>::setFloatReg(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
}
diff --git a/src/cpu/ozone/inorder_back_end.hh b/src/cpu/ozone/inorder_back_end.hh
index b2522bdc8..4fd8e02f8 100644
--- a/src/cpu/ozone/inorder_back_end.hh
+++ b/src/cpu/ozone/inorder_back_end.hh
@@ -236,25 +236,6 @@ InorderBackEnd<Impl>::read(Addr addr, T &data, unsigned flags)
*/
return fault;
}
-#if 0
-template <class Impl>
-template <class T>
-Fault
-InorderBackEnd<Impl>::read(MemReqPtr &req, T &data)
-{
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- if (req->isLocked()) {
- req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
- req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
- }
-#endif
-
- Fault error;
- error = thread->mem->read(req, data);
- data = LittleEndianGuest::gtoh(data);
- return error;
-}
-#endif
template <class Impl>
template <class T>
@@ -296,61 +277,6 @@ InorderBackEnd<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
*/
return fault;
}
-#if 0
-template <class Impl>
-template <class T>
-Fault
-InorderBackEnd<Impl>::write(MemReqPtr &req, T &data)
-{
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
- ExecContext *xc;
-
- // If this is a store conditional, act appropriately
- if (req->isLocked()) {
- xc = req->xc;
-
- if (req->isUncacheable()) {
- // Don't update result register (see stq_c in isa_desc)
- req->result = 2;
- xc->setStCondFailures(0);//Needed? [RGD]
- } else {
- bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
- Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
- req->result = lock_flag;
- if (!lock_flag ||
- ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- xc->setStCondFailures(xc->readStCondFailures() + 1);
- if (((xc->readStCondFailures()) % 100000) == 0) {
- std::cerr << "Warning: "
- << xc->readStCondFailures()
- << " consecutive store conditional failures "
- << "on cpu " << req->xc->readCpuId()
- << std::endl;
- }
- return NoFault;
- }
- else xc->setStCondFailures(0);
- }
- }
-
- // Need to clear any locked flags on other proccessors for
- // this address. Only do this for succsful Store Conditionals
- // and all other stores (WH64?). Unsuccessful Store
- // Conditionals would have returned above, and wouldn't fall
- // through.
- for (int i = 0; i < cpu->system->execContexts.size(); i++){
- xc = cpu->system->execContexts[i];
- if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
- (req->paddr & ~0xf)) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- }
- }
-
-#endif
- return thread->mem->write(req, (T)LittleEndianGuest::htog(data));
-}
-#endif
template <class Impl>
template <class T>
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index efb884325..c39bfa9cd 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -213,60 +213,63 @@ class BaseSimpleCPU : public BaseCPU
// storage (which is pretty hard to imagine they would have reason
// to do).
- uint64_t readIntReg(const StaticInst *si, int idx)
+ uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
return thread->readIntReg(si->srcRegIdx(idx));
}
- FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatReg(reg_idx, width);
}
- FloatReg readFloatReg(const StaticInst *si, int idx)
+ FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatReg(reg_idx);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
+ int width)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatRegBits(reg_idx, width);
}
- FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatRegBits(reg_idx);
}
- void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
thread->setIntReg(si->destRegIdx(idx), val);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
+ int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatReg(reg_idx, val, width);
}
- void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatReg(reg_idx, val);
}
- void setFloatRegBits(const StaticInst *si, int idx,
- FloatRegBits val, int width)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatRegBits(reg_idx, val, width);
}
- void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ void setFloatRegOperandBits(const StaticInst *si, int idx,
+ FloatRegBits val)
{
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatRegBits(reg_idx, val);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index e8757c8c2..10bbe292c 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -232,75 +232,6 @@ class SimpleThread : public ThreadState
/// Set the status to Halted.
void halt();
-/*
- template <class T>
- Fault read(RequestPtr &req, T &data)
- {
-#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
- if (req->isLocked()) {
- req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
- req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
- }
-#endif
-
- Fault error;
- error = mem->prot_read(req->paddr, data, req->size);
- data = LittleEndianGuest::gtoh(data);
- return error;
- }
-
- template <class T>
- Fault write(RequestPtr &req, T &data)
- {
-#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
- ExecContext *xc;
-
- // If this is a store conditional, act appropriately
- if (req->isLocked()) {
- xc = req->xc;
-
- if (req->isUncacheable()) {
- // Don't update result register (see stq_c in isa_desc)
- req->result = 2;
- xc->setStCondFailures(0);//Needed? [RGD]
- } else {
- bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
- Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
- req->result = lock_flag;
- if (!lock_flag ||
- ((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- xc->setStCondFailures(xc->readStCondFailures() + 1);
- if (((xc->readStCondFailures()) % 100000) == 0) {
- std::cerr << "Warning: "
- << xc->readStCondFailures()
- << " consecutive store conditional failures "
- << "on cpu " << req->xc->readCpuId()
- << std::endl;
- }
- return NoFault;
- }
- else xc->setStCondFailures(0);
- }
- }
-
- // Need to clear any locked flags on other proccessors for
- // this address. Only do this for succsful Store Conditionals
- // and all other stores (WH64?). Unsuccessful Store
- // Conditionals would have returned above, and wouldn't fall
- // through.
- for (int i = 0; i < system->execContexts.size(); i++){
- xc = system->execContexts[i];
- if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
- (req->paddr & ~0xf)) {
- xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
- }
- }
-
-#endif
- return mem->prot_write(req->paddr, (T)htog(data), req->size);
- }
-*/
virtual bool misspeculating();
Fault instRead(RequestPtr &req)
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-13 17:29:50 +0000