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-rw-r--r--src/cpu/o3/iew_impl.hh6
-rw-r--r--src/cpu/pc_event.cc6
2 files changed, 7 insertions, 5 deletions
diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 9c4b1068d..92c8875e4 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -1340,10 +1340,10 @@ DefaultIEW<Impl>::executeInsts()
fetchRedirect[tid] = true;
DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
- DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
- inst->predInstAddr(), inst->predNextInstAddr());
+ DPRINTF(IEW, "Predicted target was PC: %s.\n",
+ inst->readPredTarg());
DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
- inst->pcState(), inst->nextInstAddr());
+ inst->pcState());
// If incorrect, then signal the ROB that it must be squashed.
squashDueToBranch(inst, tid);
diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc
index f9955d014..385a83b27 100644
--- a/src/cpu/pc_event.cc
+++ b/src/cpu/pc_event.cc
@@ -84,7 +84,9 @@ PCEventQueue::schedule(PCEvent *event)
bool
PCEventQueue::doService(ThreadContext *tc)
{
- Addr pc = tc->instAddr() & ~0x3;
+ // This will fail to break on Alpha PALcode addresses, but that is
+ // a rare use case.
+ Addr pc = tc->instAddr();
int serviced = 0;
range_t range = equal_range(pc);
for (iterator i = range.first; i != range.second; ++i) {
@@ -92,7 +94,7 @@ PCEventQueue::doService(ThreadContext *tc)
// another event. This for example, prevents two invocations
// of the SkipFuncEvent. Maybe we should have separate PC
// event queues for each processor?
- if (pc != (tc->instAddr() & ~0x3))
+ if (pc != tc->instAddr())
continue;
DPRINTF(PCEvent, "PC based event serviced at %#x: %s\n",