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-rw-r--r--src/cpu/exetrace.hh2
-rw-r--r--src/cpu/inorder/comm.hh2
-rw-r--r--src/cpu/inorder/inorder_trace.hh2
-rw-r--r--src/cpu/inteltrace.hh2
-rw-r--r--src/cpu/legiontrace.hh2
-rw-r--r--src/cpu/nativetrace.hh2
-rw-r--r--src/cpu/o3/2bit_local_pred.hh2
-rw-r--r--src/cpu/o3/bpred_unit.hh2
-rw-r--r--src/cpu/o3/btb.hh2
-rw-r--r--src/cpu/o3/comm.hh2
-rw-r--r--src/cpu/o3/fetch_impl.hh2
-rw-r--r--src/cpu/o3/inst_queue.hh2
-rw-r--r--src/cpu/o3/ras.hh2
-rw-r--r--src/cpu/o3/sat_counter.hh2
-rw-r--r--src/cpu/o3/store_set.hh2
-rw-r--r--src/cpu/o3/tournament_pred.hh2
-rw-r--r--src/cpu/ozone/ea_list.hh2
-rw-r--r--src/cpu/ozone/inst_queue.hh2
-rw-r--r--src/cpu/ozone/null_predictor.hh2
-rw-r--r--src/cpu/pc_event.hh2
-rw-r--r--src/cpu/profile.hh2
-rw-r--r--src/cpu/simple/base.cc2
-rw-r--r--src/cpu/simple_thread.hh2
-rw-r--r--src/cpu/static_inst.hh2
-rw-r--r--src/cpu/thread_context.hh2
25 files changed, 25 insertions, 25 deletions
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index e49a2bb59..a1bbe3735 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -34,7 +34,7 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/insttracer.hh"
#include "params/ExeTracer.hh"
diff --git a/src/cpu/inorder/comm.hh b/src/cpu/inorder/comm.hh
index 18bb24169..1a7fc9050 100644
--- a/src/cpu/inorder/comm.hh
+++ b/src/cpu/inorder/comm.hh
@@ -39,7 +39,7 @@
#include "cpu/inorder/inorder_dyn_inst.hh"
#include "cpu/inorder/pipeline_traits.hh"
#include "cpu/inst_seq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
/** Struct that defines the information passed from in between stages */
/** This information mainly goes forward through the pipeline. */
diff --git a/src/cpu/inorder/inorder_trace.hh b/src/cpu/inorder/inorder_trace.hh
index 4338b438c..eb1287370 100644
--- a/src/cpu/inorder/inorder_trace.hh
+++ b/src/cpu/inorder/inorder_trace.hh
@@ -34,7 +34,7 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/insttracer.hh"
#include "params/InOrderTrace.hh"
#include "cpu/exetrace.hh"
diff --git a/src/cpu/inteltrace.hh b/src/cpu/inteltrace.hh
index e34658b58..56fafe93a 100644
--- a/src/cpu/inteltrace.hh
+++ b/src/cpu/inteltrace.hh
@@ -35,7 +35,7 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "params/IntelTrace.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/insttracer.hh"
class ThreadContext;
diff --git a/src/cpu/legiontrace.hh b/src/cpu/legiontrace.hh
index 9962063e4..19a996ed3 100644
--- a/src/cpu/legiontrace.hh
+++ b/src/cpu/legiontrace.hh
@@ -35,7 +35,7 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
#include "params/LegionTrace.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/insttracer.hh"
class ThreadContext;
diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh
index 9e912d92f..12d96e0ae 100644
--- a/src/cpu/nativetrace.hh
+++ b/src/cpu/nativetrace.hh
@@ -34,7 +34,7 @@
#include "base/trace.hh"
#include "cpu/static_inst.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/insttracer.hh"
#include "arch/x86/intregs.hh"
#include "arch/x86/floatregs.hh"
diff --git a/src/cpu/o3/2bit_local_pred.hh b/src/cpu/o3/2bit_local_pred.hh
index 954b86b4c..7669c6b97 100644
--- a/src/cpu/o3/2bit_local_pred.hh
+++ b/src/cpu/o3/2bit_local_pred.hh
@@ -32,7 +32,7 @@
#define __CPU_O3_2BIT_LOCAL_PRED_HH__
#include "cpu/o3/sat_counter.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include <vector>
diff --git a/src/cpu/o3/bpred_unit.hh b/src/cpu/o3/bpred_unit.hh
index a11582ca7..15d34316e 100644
--- a/src/cpu/o3/bpred_unit.hh
+++ b/src/cpu/o3/bpred_unit.hh
@@ -39,7 +39,7 @@
#include "cpu/o3/ras.hh"
#include "cpu/o3/tournament_pred.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include <list>
diff --git a/src/cpu/o3/btb.hh b/src/cpu/o3/btb.hh
index 3c4899e89..38ecabc46 100644
--- a/src/cpu/o3/btb.hh
+++ b/src/cpu/o3/btb.hh
@@ -32,7 +32,7 @@
#define __CPU_O3_BTB_HH__
#include "base/misc.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class DefaultBTB
{
diff --git a/src/cpu/o3/comm.hh b/src/cpu/o3/comm.hh
index fb772060b..a486f340d 100644
--- a/src/cpu/o3/comm.hh
+++ b/src/cpu/o3/comm.hh
@@ -35,7 +35,7 @@
#include "sim/faults.hh"
#include "cpu/inst_seq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
// Typedef for physical register index type. Although the Impl would be the
// most likely location for this, there are a few classes that need this
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 279d3e56a..96a4aebef 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -42,7 +42,7 @@
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/byteswap.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/core.hh"
#if FULL_SYSTEM
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index 0c3f44436..5537a57e7 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -42,7 +42,7 @@
#include "cpu/o3/dep_graph.hh"
#include "cpu/op_class.hh"
#include "sim/eventq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class DerivO3CPUParams;
class FUPool;
diff --git a/src/cpu/o3/ras.hh b/src/cpu/o3/ras.hh
index f0621c5b5..e9a52fd37 100644
--- a/src/cpu/o3/ras.hh
+++ b/src/cpu/o3/ras.hh
@@ -31,7 +31,7 @@
#ifndef __CPU_O3_RAS_HH__
#define __CPU_O3_RAS_HH__
-#include "sim/host.hh"
+#include "base/types.hh"
#include <vector>
/** Return address stack class, implements a simple RAS. */
diff --git a/src/cpu/o3/sat_counter.hh b/src/cpu/o3/sat_counter.hh
index 7e15119b0..7dd840f31 100644
--- a/src/cpu/o3/sat_counter.hh
+++ b/src/cpu/o3/sat_counter.hh
@@ -32,7 +32,7 @@
#define __CPU_O3_SAT_COUNTER_HH__
#include "base/misc.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
/**
* Private counter class for the internal saturating counters.
diff --git a/src/cpu/o3/store_set.hh b/src/cpu/o3/store_set.hh
index f9f7637d0..88f5e0d07 100644
--- a/src/cpu/o3/store_set.hh
+++ b/src/cpu/o3/store_set.hh
@@ -37,7 +37,7 @@
#include <vector>
#include "cpu/inst_seq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
struct ltseqnum {
bool operator()(const InstSeqNum &lhs, const InstSeqNum &rhs) const
diff --git a/src/cpu/o3/tournament_pred.hh b/src/cpu/o3/tournament_pred.hh
index 472944910..31e539628 100644
--- a/src/cpu/o3/tournament_pred.hh
+++ b/src/cpu/o3/tournament_pred.hh
@@ -32,7 +32,7 @@
#define __CPU_O3_TOURNAMENT_PRED_HH__
#include "cpu/o3/sat_counter.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include <vector>
/**
diff --git a/src/cpu/ozone/ea_list.hh b/src/cpu/ozone/ea_list.hh
index d9e9d701f..eadd577a4 100644
--- a/src/cpu/ozone/ea_list.hh
+++ b/src/cpu/ozone/ea_list.hh
@@ -36,7 +36,7 @@
#include <utility>
#include "cpu/inst_seq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
/**
* Simple class to hold onto a list of pairs, each pair having a memory
diff --git a/src/cpu/ozone/inst_queue.hh b/src/cpu/ozone/inst_queue.hh
index e840d5c21..8235760b4 100644
--- a/src/cpu/ozone/inst_queue.hh
+++ b/src/cpu/ozone/inst_queue.hh
@@ -39,7 +39,7 @@
#include "base/statistics.hh"
#include "base/timebuf.hh"
#include "cpu/inst_seq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class FUPool;
class MemInterface;
diff --git a/src/cpu/ozone/null_predictor.hh b/src/cpu/ozone/null_predictor.hh
index 0751338b7..e930ca7d4 100644
--- a/src/cpu/ozone/null_predictor.hh
+++ b/src/cpu/ozone/null_predictor.hh
@@ -32,7 +32,7 @@
#define __CPU_OZONE_NULL_PREDICTOR_HH__
#include "cpu/inst_seq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
template <class Impl>
class NullPredictor
diff --git a/src/cpu/pc_event.hh b/src/cpu/pc_event.hh
index 3709dcd59..f26bbf3f2 100644
--- a/src/cpu/pc_event.hh
+++ b/src/cpu/pc_event.hh
@@ -35,7 +35,7 @@
#include <vector>
#include "base/misc.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
class PCEventQueue;
diff --git a/src/cpu/profile.hh b/src/cpu/profile.hh
index 27bb4efec..9606ed24d 100644
--- a/src/cpu/profile.hh
+++ b/src/cpu/profile.hh
@@ -35,7 +35,7 @@
#include "arch/stacktrace.hh"
#include "cpu/static_inst.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
class ThreadContext;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 5058db0da..ef9f2e712 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -51,7 +51,7 @@
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/debug.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/sim_events.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 3daa55791..7348a8576 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -41,7 +41,7 @@
#include "mem/request.hh"
#include "sim/byteswap.hh"
#include "sim/eventq.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/serialize.hh"
class BaseCPU;
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 1dc148ce6..58a6b7986 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -43,7 +43,7 @@
#include "base/refcnt.hh"
#include "cpu/op_class.hh"
#include "sim/faults.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
// forward declarations
struct AlphaSimpleImpl;
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index ca649b40e..08b9b6e0c 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -36,7 +36,7 @@
#include "config/full_system.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
-#include "sim/host.hh"
+#include "base/types.hh"
#include "sim/serialize.hh"
#include "sim/byteswap.hh"
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 02:59:33 +0000