diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/inorder/cpu.cc | 3 | ||||
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 2 |
2 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc index 8188ac354..e8608181f 100644 --- a/src/cpu/inorder/cpu.cc +++ b/src/cpu/inorder/cpu.cc @@ -702,7 +702,10 @@ InOrderCPU::tick() ++numCycles; +#if FULL_SYSTEM checkForInterrupts(); +#endif + bool pipes_idle = true; //Tick each of the stages for (int stNum=NumStages - 1; stNum >= 0 ; stNum--) { diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 94f2d0461..350e2d1dd 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -454,8 +454,8 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size, // schedule a time to process the tlb miss. // latency hardcoded to 1 (for now), but will be updated // when timing translation gets added in - scheduleEvent(slot_idx, 1); unsigned slot_idx = cache_req->getSlot(); + scheduleEvent(slot_idx, 1); #endif // Mark it as complete so it can pass through next stage. |