diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 10 | ||||
| -rw-r--r-- | src/cpu/exetrace.cc | 2 | ||||
| -rw-r--r-- | src/cpu/inorder/resources/cache_unit.cc | 7 | ||||
| -rw-r--r-- | src/cpu/minor/lsq.cc | 2 | ||||
| -rw-r--r-- | src/cpu/simple/atomic.cc | 10 | ||||
| -rw-r--r-- | src/cpu/simple/timing.cc | 10 |
6 files changed, 17 insertions, 24 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index af4d238e2..108b799e1 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -917,9 +917,8 @@ BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, } } - if (traceData) { - traceData->setAddr(addr); - } + if (traceData) + traceData->setMem(addr, size, flags); return fault; } @@ -929,9 +928,8 @@ Fault BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, Addr addr, unsigned flags, uint64_t *res) { - if (traceData) { - traceData->setAddr(addr); - } + if (traceData) + traceData->setMem(addr, size, flags); instFlags[ReqMade] = true; Request *req = NULL; diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc index 345adbc81..dfd39d7cc 100644 --- a/src/cpu/exetrace.cc +++ b/src/cpu/exetrace.cc @@ -120,7 +120,7 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran) ccprintf(outs, " D=%#018x", data.as_int); } - if (Debug::ExecEffAddr && addr_valid) + if (Debug::ExecEffAddr && getMemValid()) outs << " A=0x" << hex << addr; if (Debug::ExecFetchSeq && fetch_seq_valid) diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 3a44986e2..f8fa3b0d3 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -425,7 +425,7 @@ CacheUnit::read(DynInstPtr inst, Addr addr, inst->totalSize = size; if (inst->traceData) { - inst->traceData->setAddr(addr); + inst->traceData->setMem(addr, size, flags); } if (inst->split2ndAccess) { @@ -519,9 +519,8 @@ CacheUnit::write(DynInstPtr inst, uint8_t *data, unsigned size, int fullSize = size; inst->totalSize = size; - if (inst->traceData) { - inst->traceData->setAddr(addr); - } + if (inst->traceData) + inst->traceData->setMem(addr, size, flags); if (inst->split2ndAccess) { size = inst->split2ndSize; diff --git a/src/cpu/minor/lsq.cc b/src/cpu/minor/lsq.cc index 28c3546b6..72873211b 100644 --- a/src/cpu/minor/lsq.cc +++ b/src/cpu/minor/lsq.cc @@ -1499,7 +1499,7 @@ LSQ::pushRequest(MinorDynInstPtr inst, bool isLoad, uint8_t *data, } if (inst->traceData) - inst->traceData->setAddr(addr); + inst->traceData->setMem(addr, size, flags); request->request.setThreadContext(cpu.cpuId(), /* thread id */ 0); request->request.setVirt(0 /* asid */, diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index d1298e3cc..b564521ba 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -317,9 +317,8 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, // use the CPU's statically allocated read request and packet objects Request *req = &data_read_req; - if (traceData) { - traceData->setAddr(addr); - } + if (traceData) + traceData->setMem(addr, size, flags); //The size of the data we're trying to read. int fullSize = size; @@ -413,9 +412,8 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, // use the CPU's statically allocated write request and packet objects Request *req = &data_write_req; - if (traceData) { - traceData->setAddr(addr); - } + if (traceData) + traceData->setMem(addr, size, flags); //The size of the data we're trying to read. int fullSize = size; diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 8c90d7c4e..6de6899e7 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -402,9 +402,8 @@ TimingSimpleCPU::readMem(Addr addr, uint8_t *data, unsigned block_size = cacheLineSize(); BaseTLB::Mode mode = BaseTLB::Read; - if (traceData) { - traceData->setAddr(addr); - } + if (traceData) + traceData->setMem(addr, size, flags); RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, _cpuId, tid); @@ -479,9 +478,8 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, memcpy(newData, data, size); } - if (traceData) { - traceData->setAddr(addr); - } + if (traceData) + traceData->setMem(addr, size, flags); RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, _cpuId, tid); |