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-rw-r--r--src/cpu/o3/fetch_impl.hh2
-rw-r--r--src/cpu/simple/atomic.cc6
-rw-r--r--src/cpu/simple/base.cc10
3 files changed, 9 insertions, 9 deletions
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index ab55ec744..1ce5bd20f 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1128,7 +1128,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
(&cacheData[tid][offset]));
predecoder.setTC(cpu->thread[tid]->getTC());
- predecoder.moreBytes(fetch_PC, fetch_PC, 0, inst);
+ predecoder.moreBytes(fetch_PC, fetch_PC, inst);
ext_inst = predecoder.getExtMachInst();
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index ea1c7d87f..03ff1282b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -521,15 +521,15 @@ AtomicSimpleCPU::tick()
dcache_access = false; // assume no dcache access
//Fetch more instruction memory if necessary
- if(predecoder.needMoreBytes())
- {
+ //if(predecoder.needMoreBytes())
+ //{
icache_access = true;
ifetch_pkt->reinitFromRequest();
icache_latency = icachePort.sendAtomic(ifetch_pkt);
// ifetch_req is initialized to read the instruction directly
// into the CPU object's inst field.
- }
+ //}
preExecute();
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index b7f60522f..9285aa7b5 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -379,11 +379,11 @@ BaseSimpleCPU::preExecute()
//This should go away once the constructor can be set up properly
predecoder.setTC(thread->getTC());
//If more fetch data is needed, pass it in.
- if(predecoder.needMoreBytes())
- predecoder.moreBytes(thread->readPC(),
- (thread->readPC() & PCMask) + fetchOffset, 0, inst);
- else
- predecoder.process();
+ Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset;
+ //if(predecoder.needMoreBytes())
+ predecoder.moreBytes(thread->readPC(), fetchPC, inst);
+ //else
+ // predecoder.process();
//If an instruction is ready, decode it. Otherwise, we'll have to
//fetch beyond the MachInst at the current pc.