diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/base_dyn_inst.hh | 4 | ||||
| -rw-r--r-- | src/cpu/o3/fetch_impl.hh | 2 | ||||
| -rw-r--r-- | src/cpu/simple/atomic.cc | 3 | ||||
| -rw-r--r-- | src/cpu/simple/timing.cc | 5 |
4 files changed, 14 insertions, 0 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index b7b076820..f12a89bbd 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -890,6 +890,8 @@ BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), thread->contextId(), threadNumber); + req->taskId(cpu->taskId()); + // Only split the request if the ISA supports unaligned accesses. if (TheISA::HasUnalignedMemAcc) { splitRequest(req, sreqLow, sreqHigh); @@ -953,6 +955,8 @@ BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), thread->contextId(), threadNumber); + req->taskId(cpu->taskId()); + // Only split the request if the ISA supports unaligned accesses. if (TheISA::HasUnalignedMemAcc) { splitRequest(req, sreqLow, sreqHigh); diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 5b04c2a25..a81125da6 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -604,6 +604,8 @@ DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) Request::INST_FETCH, cpu->instMasterId(), pc, cpu->thread[tid]->contextId(), tid); + mem_req->taskId(cpu->taskId()); + memReq[tid] = mem_req; // Initiate translation of the icache block diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 13c4b9bd3..617e845a5 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -301,6 +301,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, dcache_latency = 0; + req->taskId(taskId()); while (1) { req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); @@ -387,6 +388,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, dcache_latency = 0; + req->taskId(taskId()); while(1) { req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); @@ -492,6 +494,7 @@ AtomicSimpleCPU::tick() bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; if (needToFetch) { + ifetch_req.taskId(taskId()); setupFetchRequest(&ifetch_req); fault = thread->itb->translateAtomic(&ifetch_req, tc, BaseTLB::Execute); diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 9253d8005..7996a6ddd 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -415,6 +415,8 @@ TimingSimpleCPU::readMem(Addr addr, uint8_t *data, RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, _cpuId, tid); + req->taskId(taskId()); + Addr split_addr = roundDown(addr + size - 1, block_size); assert(split_addr <= addr || split_addr - addr < block_size); @@ -484,6 +486,8 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, _cpuId, tid); + req->taskId(taskId()); + Addr split_addr = roundDown(addr + size - 1, block_size); assert(split_addr <= addr || split_addr - addr < block_size); @@ -561,6 +565,7 @@ TimingSimpleCPU::fetch() if (needToFetch) { _status = BaseSimpleCPU::Running; Request *ifetch_req = new Request(); + ifetch_req->taskId(taskId()); ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); setupFetchRequest(ifetch_req); DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); |