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-rw-r--r--src/cpu/base.cc4
-rw-r--r--src/cpu/base.hh2
-rw-r--r--src/cpu/checker/cpu.hh15
-rw-r--r--src/cpu/checker/thread_context.hh4
-rw-r--r--src/cpu/o3/cpu.hh4
-rw-r--r--src/cpu/o3/fetch_impl.hh2
-rwxr-xr-xsrc/cpu/o3/thread_context.hh4
-rw-r--r--src/cpu/simple/base.cc1
-rw-r--r--src/cpu/simple_thread.cc6
-rw-r--r--src/cpu/simple_thread.hh14
-rw-r--r--src/cpu/thread_context.hh10
11 files changed, 30 insertions, 36 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 2c3ca0809..4fd804b9c 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -51,7 +51,7 @@
#include <sstream>
#include <string>
-#include "arch/tlb.hh"
+#include "arch/generic/tlb.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "base/logging.hh"
@@ -313,7 +313,7 @@ BaseCPU::mwait(ThreadID tid, PacketPtr pkt)
}
void
-BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, TheISA::TLB *dtb)
+BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb)
{
assert(tid < numThreads);
AddressMonitor &monitor = addressMonitor[tid];
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 52598fd22..8673d2330 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -626,7 +626,7 @@ class BaseCPU : public MemObject
public:
void armMonitor(ThreadID tid, Addr address);
bool mwait(ThreadID tid, PacketPtr pkt);
- void mwaitAtomic(ThreadID tid, ThreadContext *tc, TheISA::TLB *dtb);
+ void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb);
AddressMonitor *getCpuAddrMonitor(ThreadID tid)
{
assert(tid < numThreads);
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 213106bd2..b1a457491 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -62,12 +62,7 @@
#include "params/CheckerCPU.hh"
#include "sim/eventq.hh"
-// forward declarations
-namespace TheISA
-{
- class TLB;
-}
-
+class BaseTLB;
template <class>
class BaseDynInst;
class ThreadContext;
@@ -140,8 +135,8 @@ class CheckerCPU : public BaseCPU, public ExecContext
ThreadContext *tc;
- TheISA::TLB *itb;
- TheISA::TLB *dtb;
+ BaseTLB *itb;
+ BaseTLB *dtb;
Addr dbg_vtophys(Addr addr);
@@ -166,8 +161,8 @@ class CheckerCPU : public BaseCPU, public ExecContext
// Primary thread being run.
SimpleThread *thread;
- TheISA::TLB* getITBPtr() { return itb; }
- TheISA::TLB* getDTBPtr() { return dtb; }
+ BaseTLB* getITBPtr() { return itb; }
+ BaseTLB* getDTBPtr() { return dtb; }
virtual Counter totalInsts() const override
{
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 5208932de..975bd9f96 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -112,9 +112,9 @@ class CheckerThreadContext : public ThreadContext
actualTC->setThreadId(id);
}
- TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
+ BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
- TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
+ BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
CheckerCPU *getCheckerCpuPtr()
{
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 28ccd15b0..10af087d1 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -123,8 +123,8 @@ class FullO3CPU : public BaseO3CPU
SwitchedOut
};
- TheISA::TLB * itb;
- TheISA::TLB * dtb;
+ BaseTLB *itb;
+ BaseTLB *dtb;
/** Overall CPU status. */
Status _status;
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 0cf8a47a7..6cca77a87 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -51,8 +51,8 @@
#include <map>
#include <queue>
+#include "arch/generic/tlb.hh"
#include "arch/isa_traits.hh"
-#include "arch/tlb.hh"
#include "arch/utility.hh"
#include "arch/vtophys.hh"
#include "base/random.hh"
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index ac4ceed02..2256a8a14 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -79,10 +79,10 @@ class O3ThreadContext : public ThreadContext
O3ThreadState<Impl> *thread;
/** Returns a pointer to the ITB. */
- TheISA::TLB *getITBPtr() { return cpu->itb; }
+ BaseTLB *getITBPtr() { return cpu->itb; }
/** Returns a pointer to the DTB. */
- TheISA::TLB *getDTBPtr() { return cpu->dtb; }
+ BaseTLB *getDTBPtr() { return cpu->dtb; }
CheckerCPU *getCheckerCpuPtr() { return NULL; }
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 1f12afbf0..36a2cb06c 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -45,7 +45,6 @@
#include "arch/kernel_stats.hh"
#include "arch/stacktrace.hh"
-#include "arch/tlb.hh"
#include "arch/utility.hh"
#include "arch/vtophys.hh"
#include "base/cp_annotate.hh"
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index c775983f8..f86acedd6 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -62,8 +62,8 @@ using namespace std;
// constructor
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
- Process *_process, TheISA::TLB *_itb,
- TheISA::TLB *_dtb, TheISA::ISA *_isa)
+ Process *_process, BaseTLB *_itb,
+ BaseTLB *_dtb, TheISA::ISA *_isa)
: ThreadState(_cpu, _thread_num, _process), isa(_isa),
predicate(false), system(_sys),
itb(_itb), dtb(_dtb)
@@ -74,7 +74,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
}
SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
- TheISA::TLB *_itb, TheISA::TLB *_dtb,
+ BaseTLB *_itb, BaseTLB *_dtb,
TheISA::ISA *_isa, bool use_kernel_stats)
: ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
dtb(_dtb)
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 4ea8b91ba..3c64082b8 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -46,10 +46,10 @@
#define __CPU_SIMPLE_THREAD_HH__
#include "arch/decoder.hh"
+#include "arch/generic/tlb.hh"
#include "arch/isa.hh"
#include "arch/isa_traits.hh"
#include "arch/registers.hh"
-#include "arch/tlb.hh"
#include "arch/types.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
@@ -135,19 +135,19 @@ class SimpleThread : public ThreadState
System *system;
- TheISA::TLB *itb;
- TheISA::TLB *dtb;
+ BaseTLB *itb;
+ BaseTLB *dtb;
TheISA::Decoder decoder;
// constructor: initialize SimpleThread from given process structure
// FS
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
- TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa,
+ BaseTLB *_itb, BaseTLB *_dtb, TheISA::ISA *_isa,
bool use_kernel_stats = true);
// SE
SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
- Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb,
+ Process *_process, BaseTLB *_itb, BaseTLB *_dtb,
TheISA::ISA *_isa);
virtual ~SimpleThread();
@@ -201,9 +201,9 @@ class SimpleThread : public ThreadState
BaseCPU *getCpuPtr() { return baseCpu; }
- TheISA::TLB *getITBPtr() { return itb; }
+ BaseTLB *getITBPtr() { return itb; }
- TheISA::TLB *getDTBPtr() { return dtb; }
+ BaseTLB *getDTBPtr() { return dtb; }
CheckerCPU *getCheckerCpuPtr() { return NULL; }
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 66b2f7554..1e3064956 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -58,9 +58,9 @@
namespace TheISA
{
class Decoder;
- class TLB;
}
class BaseCPU;
+class BaseTLB;
class CheckerCPU;
class Checkpoint;
class EndQuiesceEvent;
@@ -136,9 +136,9 @@ class ThreadContext
virtual void setContextId(int id) = 0;
- virtual TheISA::TLB *getITBPtr() = 0;
+ virtual BaseTLB *getITBPtr() = 0;
- virtual TheISA::TLB *getDTBPtr() = 0;
+ virtual BaseTLB *getDTBPtr() = 0;
virtual CheckerCPU *getCheckerCpuPtr() = 0;
@@ -394,9 +394,9 @@ class ProxyThreadContext : public ThreadContext
void setContextId(int id) { actualTC->setContextId(id); }
- TheISA::TLB *getITBPtr() { return actualTC->getITBPtr(); }
+ BaseTLB *getITBPtr() { return actualTC->getITBPtr(); }
- TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
+ BaseTLB *getDTBPtr() { return actualTC->getDTBPtr(); }
CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-20 02:53:21 +0000