diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/o3/rename_impl.hh | 6 | ||||
| -rwxr-xr-x | src/cpu/o3/thread_context_impl.hh | 8 | ||||
| -rw-r--r-- | src/cpu/simple_thread.hh | 30 |
3 files changed, 32 insertions, 12 deletions
diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index d78de2c87..49c885753 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -959,9 +959,11 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst,unsigned tid) if (src_reg < TheISA::FP_Base_DepTag) { flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); + } else if (src_reg < TheISA::Ctrl_Base_DepTag) { + src_reg = src_reg - TheISA::FP_Base_DepTag; + flat_src_reg = TheISA::flattenFloatIndex(inst->tcBase(), src_reg); + flat_src_reg += TheISA::NumIntRegs; } else { - // Floating point and Miscellaneous registers need their indexes - // adjusted to account for the expanded number of flattened int regs. flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; DPRINTF(Rename, "Adjusting reg index from %d to %d.\n", src_reg, flat_src_reg); } diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index a145e046e..efbbc2329 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -314,6 +314,7 @@ template <class Impl> TheISA::FloatReg O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); switch(width) { case 32: return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); @@ -329,6 +330,7 @@ template <class Impl> TheISA::FloatReg O3ThreadContext<Impl>::readFloatReg(int reg_idx) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); } @@ -337,6 +339,7 @@ TheISA::FloatRegBits O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width) { DPRINTF(Fault, "Reading floatint register through the TC!\n"); + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); } @@ -344,6 +347,7 @@ template <class Impl> TheISA::FloatRegBits O3ThreadContext<Impl>::readFloatRegBits(int reg_idx) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); } @@ -364,6 +368,7 @@ template <class Impl> void O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); switch(width) { case 32: cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); @@ -383,6 +388,7 @@ template <class Impl> void O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); if (!thread->trapPending && !thread->inSyscall) { @@ -396,6 +402,7 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val, int width) { DPRINTF(Fault, "Setting floatint register through the TC!\n"); + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); // Squash if we're not already in a state update mode. @@ -408,6 +415,7 @@ template <class Impl> void O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val) { + reg_idx = TheISA::flattenFloatIndex(this, reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); // Squash if we're not already in a state update mode. diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 1e87b0bb7..c018e3e49 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -235,52 +235,62 @@ class SimpleThread : public ThreadState // uint64_t readIntReg(int reg_idx) { - return regs.readIntReg(TheISA::flattenIntIndex(getTC(), reg_idx)); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + return regs.readIntReg(flatIndex); } FloatReg readFloatReg(int reg_idx, int width) { - return regs.readFloatReg(reg_idx, width); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + return regs.readFloatReg(flatIndex, width); } FloatReg readFloatReg(int reg_idx) { - return regs.readFloatReg(reg_idx); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + return regs.readFloatReg(flatIndex); } FloatRegBits readFloatRegBits(int reg_idx, int width) { - return regs.readFloatRegBits(reg_idx, width); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + return regs.readFloatRegBits(flatIndex, width); } FloatRegBits readFloatRegBits(int reg_idx) { - return regs.readFloatRegBits(reg_idx); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + return regs.readFloatRegBits(flatIndex); } void setIntReg(int reg_idx, uint64_t val) { - regs.setIntReg(TheISA::flattenIntIndex(getTC(), reg_idx), val); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + regs.setIntReg(flatIndex, val); } void setFloatReg(int reg_idx, FloatReg val, int width) { - regs.setFloatReg(reg_idx, val, width); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + regs.setFloatReg(flatIndex, val, width); } void setFloatReg(int reg_idx, FloatReg val) { - regs.setFloatReg(reg_idx, val); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + regs.setFloatReg(flatIndex, val); } void setFloatRegBits(int reg_idx, FloatRegBits val, int width) { - regs.setFloatRegBits(reg_idx, val, width); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + regs.setFloatRegBits(flatIndex, val, width); } void setFloatRegBits(int reg_idx, FloatRegBits val) { - regs.setFloatRegBits(reg_idx, val); + int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx); + regs.setFloatRegBits(flatIndex, val); } uint64_t readPC() |