diff options
Diffstat (limited to 'src/cpu')
| -rw-r--r-- | src/cpu/BaseCPU.py | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index cb5793e57..9fc1db9f1 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -101,9 +101,7 @@ class BaseCPU(SimObject): _mem_ports = [] if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: - itb.walker_port = Port("ITB page table walker port") - dtb.walker_port = Port("ITB page table walker port") - _mem_ports = ["itb.walker_port", "dtb.walker_port"] + _mem_ports = ["itb.walker.port", "dtb.walker.port"] def connectMemPorts(self, bus): for p in self._mem_ports: |