summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu')
-rw-r--r--src/cpu/exetrace.cc46
-rw-r--r--src/cpu/exetrace.hh22
-rw-r--r--src/cpu/simple/base.cc2
3 files changed, 21 insertions, 49 deletions
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index 0008035c2..ad802eba2 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -66,20 +66,19 @@ Trace::InstRecord::dump(ostream &outs)
static const char * prefixes[4] = {"G", "O", "L", "I"};
if (flags[PRINT_REG_DELTA])
{
- ThreadContext * context = cpu->threadContexts[0];
char buf[256];
- sprintf(buf, "PC = 0x%016llx", context->readNextPC());
+ sprintf(buf, "PC = 0x%016llx", thread->readNextPC());
outs << buf;
- sprintf(buf, " NPC = 0x%016llx", context->readNextNPC());
+ sprintf(buf, " NPC = 0x%016llx", thread->readNextNPC());
outs << buf;
- newVal = context->readMiscReg(SparcISA::MISCREG_CCR);
+ newVal = thread->readMiscReg(SparcISA::MISCREG_CCR);
if(newVal != ccr)
{
sprintf(buf, " CCR = 0x%016llx", newVal);
outs << buf;
ccr = newVal;
}
- newVal = context->readMiscReg(SparcISA::MISCREG_Y);
+ newVal = thread->readMiscReg(SparcISA::MISCREG_Y);
if(newVal != y)
{
sprintf(buf, " Y = 0x%016llx", newVal);
@@ -91,7 +90,7 @@ Trace::InstRecord::dump(ostream &outs)
for(int x = 0; x < 8; x++)
{
int index = x + 8 * y;
- newVal = context->readIntReg(index);
+ newVal = thread->readIntReg(index);
if(regs[index] != newVal)
{
sprintf(buf, " %s%d = 0x%016llx", prefixes[y], x, newVal);
@@ -102,7 +101,7 @@ Trace::InstRecord::dump(ostream &outs)
}
for(int y = 0; y < 32; y++)
{
- newVal = context->readFloatRegBits(2 * y, 64);
+ newVal = thread->readFloatRegBits(2 * y, 64);
if(floats[y] != newVal)
{
sprintf(buf, " F%d = 0x%016llx", y, newVal);
@@ -111,37 +110,10 @@ Trace::InstRecord::dump(ostream &outs)
}
}
outs << endl;
- /*
- int numSources = staticInst->numSrcRegs();
- int numDests = staticInst->numDestRegs();
- outs << "Sources:";
- for(int x = 0; x < numSources; x++)
- {
- int sourceNum = staticInst->srcRegIdx(x);
- if(sourceNum < FP_Base_DepTag)
- outs << " " << getIntRegName(sourceNum);
- else if(sourceNum < Ctrl_Base_DepTag)
- outs << " " << getFloatRegName(sourceNum - FP_Base_DepTag);
- else
- outs << " " << getMiscRegName(sourceNum - Ctrl_Base_DepTag);
- }
- outs << endl;
- outs << "Destinations:";
- for(int x = 0; x < numDests; x++)
- {
- int destNum = staticInst->destRegIdx(x);
- if(destNum < FP_Base_DepTag)
- outs << " " << getIntRegName(destNum);
- else if(destNum < Ctrl_Base_DepTag)
- outs << " " << getFloatRegName(destNum - FP_Base_DepTag);
- else
- outs << " " << getMiscRegName(destNum - Ctrl_Base_DepTag);
- }
- outs << endl;*/
}
else if (flags[INTEL_FORMAT]) {
#if FULL_SYSTEM
- bool is_trace_system = (cpu->system->name() == trace_system);
+ bool is_trace_system = (thread->getCpuPtr()->system->name() == trace_system);
#else
bool is_trace_system = true;
#endif
@@ -161,13 +133,13 @@ Trace::InstRecord::dump(ostream &outs)
if (flags[PRINT_CYCLE])
ccprintf(outs, "%7d: ", cycle);
- outs << cpu->name() << " ";
+ outs << thread->getCpuPtr()->name() << " ";
if (flags[TRACE_MISSPEC])
outs << (misspeculating ? "-" : "+") << " ";
if (flags[PRINT_THREAD_NUM])
- outs << "T" << thread << " : ";
+ outs << "T" << thread->getThreadNum() << " : ";
std::string sym_str;
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index 8cc98b777..02ea162f0 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -41,7 +41,7 @@
#include "cpu/thread_context.hh"
#include "cpu/static_inst.hh"
-class BaseCPU;
+class ThreadContext;
namespace Trace {
@@ -53,13 +53,12 @@ class InstRecord : public Record
// The following fields are initialized by the constructor and
// thus guaranteed to be valid.
- BaseCPU *cpu;
+ ThreadContext *thread;
// need to make this ref-counted so it doesn't go away before we
// dump the record
StaticInstPtr staticInst;
Addr PC;
bool misspeculating;
- unsigned thread;
// The remaining fields are only valid for particular instruction
// types (e.g, addresses for memory ops) or when particular
@@ -95,11 +94,12 @@ class InstRecord : public Record
bool regs_valid;
public:
- InstRecord(Tick _cycle, BaseCPU *_cpu,
+ InstRecord(Tick _cycle, ThreadContext *_thread,
const StaticInstPtr &_staticInst,
- Addr _pc, bool spec, int _thread)
- : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
- misspeculating(spec), thread(_thread)
+ Addr _pc, bool spec)
+ : Record(_cycle), thread(_thread),
+ staticInst(_staticInst), PC(_pc),
+ misspeculating(spec)
{
data_status = DataInvalid;
addr_valid = false;
@@ -174,14 +174,14 @@ InstRecord::setRegs(const IntRegFile &regs)
inline
InstRecord *
-getInstRecord(Tick cycle, ThreadContext *tc, BaseCPU *cpu,
+getInstRecord(Tick cycle, ThreadContext *tc,
const StaticInstPtr staticInst,
- Addr pc, int thread = 0)
+ Addr pc)
{
if (DTRACE(InstExec) &&
(InstRecord::traceMisspec() || !tc->misspeculating())) {
- return new InstRecord(cycle, cpu, staticInst, pc,
- tc->misspeculating(), thread);
+ return new InstRecord(cycle, tc, staticInst, pc,
+ tc->misspeculating());
}
return NULL;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 801c96c88..b7cfddcb8 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -398,7 +398,7 @@ BaseSimpleCPU::preExecute()
inst = gtoh(inst);
curStaticInst = StaticInst::decode(makeExtMI(inst, thread->readPC()));
- traceData = Trace::getInstRecord(curTick, tc, this, curStaticInst,
+ traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
thread->readPC());
DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 05:28:26 +0000