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-rw-r--r--src/cpu/SConscript54
-rw-r--r--src/cpu/inorder/SConscript44
-rwxr-xr-xsrc/cpu/o3/SConscript24
-rw-r--r--src/cpu/ozone/SConscript10
-rw-r--r--src/cpu/pred/SConscript2
-rw-r--r--src/cpu/simple/SConscript2
-rw-r--r--src/cpu/testers/directedtest/SConscript2
-rw-r--r--src/cpu/testers/memtest/SConscript2
-rw-r--r--src/cpu/testers/networktest/SConscript2
-rw-r--r--src/cpu/testers/rubytest/SConscript2
10 files changed, 72 insertions, 72 deletions
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index f6ed80680..edb4b2702 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -137,7 +137,7 @@ if env['FULL_SYSTEM']:
if env['USE_CHECKER']:
Source('checker/cpu.cc')
- TraceFlag('Checker')
+ DebugFlag('Checker')
checker_supports = False
for i in CheckerSupportedCPUList:
if i in env['CPU_MODELS']:
@@ -149,32 +149,32 @@ if env['USE_CHECKER']:
print ", please set USE_CHECKER=False or use one of those CPU models"
Exit(1)
-TraceFlag('Activity')
-TraceFlag('Commit')
-TraceFlag('Context')
-TraceFlag('Decode')
-TraceFlag('DynInst')
-TraceFlag('ExecEnable')
-TraceFlag('ExecCPSeq')
-TraceFlag('ExecEffAddr')
-TraceFlag('ExecFaulting', 'Trace faulting instructions')
-TraceFlag('ExecFetchSeq')
-TraceFlag('ExecOpClass')
-TraceFlag('ExecRegDelta')
-TraceFlag('ExecResult')
-TraceFlag('ExecSpeculative')
-TraceFlag('ExecSymbol')
-TraceFlag('ExecThread')
-TraceFlag('ExecTicks')
-TraceFlag('ExecMicro')
-TraceFlag('ExecMacro')
-TraceFlag('ExecUser')
-TraceFlag('ExecKernel')
-TraceFlag('ExecAsid')
-TraceFlag('Fetch')
-TraceFlag('IntrControl')
-TraceFlag('PCEvent')
-TraceFlag('Quiesce')
+DebugFlag('Activity')
+DebugFlag('Commit')
+DebugFlag('Context')
+DebugFlag('Decode')
+DebugFlag('DynInst')
+DebugFlag('ExecEnable')
+DebugFlag('ExecCPSeq')
+DebugFlag('ExecEffAddr')
+DebugFlag('ExecFaulting', 'Trace faulting instructions')
+DebugFlag('ExecFetchSeq')
+DebugFlag('ExecOpClass')
+DebugFlag('ExecRegDelta')
+DebugFlag('ExecResult')
+DebugFlag('ExecSpeculative')
+DebugFlag('ExecSymbol')
+DebugFlag('ExecThread')
+DebugFlag('ExecTicks')
+DebugFlag('ExecMicro')
+DebugFlag('ExecMacro')
+DebugFlag('ExecUser')
+DebugFlag('ExecKernel')
+DebugFlag('ExecAsid')
+DebugFlag('Fetch')
+DebugFlag('IntrControl')
+DebugFlag('PCEvent')
+DebugFlag('Quiesce')
CompoundFlag('ExecAll', [ 'ExecEnable', 'ExecCPSeq', 'ExecEffAddr',
'ExecFaulting', 'ExecFetchSeq', 'ExecOpClass', 'ExecRegDelta',
diff --git a/src/cpu/inorder/SConscript b/src/cpu/inorder/SConscript
index b9c526763..aa579a179 100644
--- a/src/cpu/inorder/SConscript
+++ b/src/cpu/inorder/SConscript
@@ -34,28 +34,28 @@ if 'InOrderCPU' in env['CPU_MODELS']:
SimObject('InOrderCPU.py')
SimObject('InOrderTrace.py')
- TraceFlag('ResReqCount')
- TraceFlag('InOrderStage')
- TraceFlag('InOrderStall')
- TraceFlag('InOrderCPU')
- TraceFlag('RegDepMap')
- TraceFlag('InOrderDynInst')
- TraceFlag('Resource')
- TraceFlag('InOrderAGEN')
- TraceFlag('InOrderFetchSeq')
- TraceFlag('InOrderTLB')
- TraceFlag('InOrderCachePort')
- TraceFlag('InOrderBPred')
- TraceFlag('InOrderDecode')
- TraceFlag('InOrderExecute')
- TraceFlag('InOrderInstBuffer')
- TraceFlag('InOrderUseDef')
- TraceFlag('InOrderMDU')
- TraceFlag('InOrderGraduation')
- TraceFlag('ThreadModel')
- TraceFlag('RefCount')
- TraceFlag('AddrDep')
- TraceFlag('SkedCache')
+ DebugFlag('ResReqCount')
+ DebugFlag('InOrderStage')
+ DebugFlag('InOrderStall')
+ DebugFlag('InOrderCPU')
+ DebugFlag('RegDepMap')
+ DebugFlag('InOrderDynInst')
+ DebugFlag('Resource')
+ DebugFlag('InOrderAGEN')
+ DebugFlag('InOrderFetchSeq')
+ DebugFlag('InOrderTLB')
+ DebugFlag('InOrderCachePort')
+ DebugFlag('InOrderBPred')
+ DebugFlag('InOrderDecode')
+ DebugFlag('InOrderExecute')
+ DebugFlag('InOrderInstBuffer')
+ DebugFlag('InOrderUseDef')
+ DebugFlag('InOrderMDU')
+ DebugFlag('InOrderGraduation')
+ DebugFlag('ThreadModel')
+ DebugFlag('RefCount')
+ DebugFlag('AddrDep')
+ DebugFlag('SkedCache')
CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU',
'InOrderMDU', 'InOrderAGEN', 'InOrderFetchSeq', 'InOrderTLB', 'InOrderBPred',
diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index 6c679e929..8ed337c25 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -33,9 +33,9 @@ import sys
Import('*')
if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
- TraceFlag('CommitRate')
- TraceFlag('IEW')
- TraceFlag('IQ')
+ DebugFlag('CommitRate')
+ DebugFlag('IEW')
+ DebugFlag('IQ')
if 'O3CPU' in env['CPU_MODELS']:
SimObject('FUPool.py')
@@ -64,15 +64,15 @@ if 'O3CPU' in env['CPU_MODELS']:
Source('store_set.cc')
Source('thread_context.cc')
- TraceFlag('LSQ')
- TraceFlag('LSQUnit')
- TraceFlag('MemDepUnit')
- TraceFlag('O3CPU')
- TraceFlag('ROB')
- TraceFlag('Rename')
- TraceFlag('Scoreboard')
- TraceFlag('StoreSet')
- TraceFlag('Writeback')
+ DebugFlag('LSQ')
+ DebugFlag('LSQUnit')
+ DebugFlag('MemDepUnit')
+ DebugFlag('O3CPU')
+ DebugFlag('ROB')
+ DebugFlag('Rename')
+ DebugFlag('Scoreboard')
+ DebugFlag('StoreSet')
+ DebugFlag('Writeback')
CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
diff --git a/src/cpu/ozone/SConscript b/src/cpu/ozone/SConscript
index 0ca1a0d07..d26410ac2 100644
--- a/src/cpu/ozone/SConscript
+++ b/src/cpu/ozone/SConscript
@@ -45,11 +45,11 @@ if 'OzoneCPU' in env['CPU_MODELS']:
Source('lw_lsq.cc')
Source('rename_table.cc')
- TraceFlag('BE')
- TraceFlag('FE')
- TraceFlag('IBE')
- TraceFlag('OzoneCPU')
- TraceFlag('OzoneLSQ')
+ DebugFlag('BE')
+ DebugFlag('FE')
+ DebugFlag('IBE')
+ DebugFlag('OzoneCPU')
+ DebugFlag('OzoneLSQ')
CompoundFlag('OzoneCPUAll', [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU' ])
diff --git a/src/cpu/pred/SConscript b/src/cpu/pred/SConscript
index ce1dab9e2..742c132c7 100644
--- a/src/cpu/pred/SConscript
+++ b/src/cpu/pred/SConscript
@@ -35,4 +35,4 @@ if 'InOrderCPU' in env['CPU_MODELS'] or 'O3CPU' in env['CPU_MODELS']:
Source('btb.cc')
Source('ras.cc')
Source('tournament.cc')
- TraceFlag('FreeList')
+ DebugFlag('FreeList')
diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript
index 76598666f..3b6b19c51 100644
--- a/src/cpu/simple/SConscript
+++ b/src/cpu/simple/SConscript
@@ -43,7 +43,7 @@ if 'TimingSimpleCPU' in env['CPU_MODELS']:
if 'AtomicSimpleCPU' in env['CPU_MODELS'] or \
'TimingSimpleCPU' in env['CPU_MODELS']:
- TraceFlag('SimpleCPU')
+ DebugFlag('SimpleCPU')
if need_simple_base:
Source('base.cc')
diff --git a/src/cpu/testers/directedtest/SConscript b/src/cpu/testers/directedtest/SConscript
index 1afa15984..a321a404c 100644
--- a/src/cpu/testers/directedtest/SConscript
+++ b/src/cpu/testers/directedtest/SConscript
@@ -45,4 +45,4 @@ Source('DirectedGenerator.cc')
Source('SeriesRequestGenerator.cc')
Source('InvalidateGenerator.cc')
-TraceFlag('DirectedTest')
+DebugFlag('DirectedTest')
diff --git a/src/cpu/testers/memtest/SConscript b/src/cpu/testers/memtest/SConscript
index 61aa0969e..566c4f2e4 100644
--- a/src/cpu/testers/memtest/SConscript
+++ b/src/cpu/testers/memtest/SConscript
@@ -35,4 +35,4 @@ SimObject('MemTest.py')
Source('memtest.cc')
-TraceFlag('MemTest')
+DebugFlag('MemTest')
diff --git a/src/cpu/testers/networktest/SConscript b/src/cpu/testers/networktest/SConscript
index b658ac079..5b6b18d42 100644
--- a/src/cpu/testers/networktest/SConscript
+++ b/src/cpu/testers/networktest/SConscript
@@ -34,4 +34,4 @@ SimObject('NetworkTest.py')
Source('networktest.cc', Werror=False)
-TraceFlag('NetworkTest')
+DebugFlag('NetworkTest')
diff --git a/src/cpu/testers/rubytest/SConscript b/src/cpu/testers/rubytest/SConscript
index 9352dd793..1b65932e7 100644
--- a/src/cpu/testers/rubytest/SConscript
+++ b/src/cpu/testers/rubytest/SConscript
@@ -44,4 +44,4 @@ Source('RubyTester.cc')
Source('Check.cc')
Source('CheckTable.cc')
-TraceFlag('RubyTest')
+DebugFlag('RubyTest')
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 00:38:13 +0000