diff options
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/BaseCPU.py | 67 | ||||
-rw-r--r-- | src/cpu/base.hh | 71 | ||||
-rwxr-xr-x | src/cpu/o3/thread_context.hh | 11 | ||||
-rw-r--r-- | src/cpu/simple/base.cc | 36 | ||||
-rw-r--r-- | src/cpu/simple/base.hh | 6 | ||||
-rw-r--r-- | src/cpu/simple_thread.hh | 4 | ||||
-rw-r--r-- | src/cpu/static_inst.hh | 3 | ||||
-rw-r--r-- | src/cpu/thread_context.hh | 22 |
8 files changed, 186 insertions, 34 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 9fc1db9f1..691f92e2e 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -44,7 +44,7 @@ elif build_env['TARGET_ISA'] == 'sparc': elif build_env['TARGET_ISA'] == 'x86': from X86TLB import X86DTB, X86ITB elif build_env['TARGET_ISA'] == 'mips': - from MipsTLB import MipsDTB, MipsITB + from MipsTLB import MipsTLB,MipsDTB, MipsITB, MipsUTB class BaseCPU(SimObject): type = 'BaseCPU' @@ -72,8 +72,10 @@ class BaseCPU(SimObject): dtb = Param.X86DTB(X86DTB(), "Data TLB") itb = Param.X86ITB(X86ITB(), "Instruction TLB") elif build_env['TARGET_ISA'] == 'mips': + UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") dtb = Param.MipsDTB(MipsDTB(), "Data TLB") itb = Param.MipsITB(MipsITB(), "Instruction TLB") + tlb = Param.MipsUTB(MipsUTB(), "Unified TLB") else: print "Don't know what TLB to use for ISA %s" % \ build_env['TARGET_ISA'] @@ -100,23 +102,18 @@ class BaseCPU(SimObject): _mem_ports = [] - if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: - _mem_ports = ["itb.walker.port", "dtb.walker.port"] - def connectMemPorts(self, bus): for p in self._mem_ports: if p != 'physmem_port': exec('self.%s = bus.port' % p) def addPrivateSplitL1Caches(self, ic, dc): - assert(len(self._mem_ports) < 6) + assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3) self.icache = ic self.dcache = dc self.icache_port = ic.cpu_side self.dcache_port = dc.cpu_side self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] - if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: - self._mem_ports += ["itb.walker_port", "dtb.walker_port"] def addTwoLevelCacheHierarchy(self, ic, dc, l2c): self.addPrivateSplitL1Caches(ic, dc) @@ -125,3 +122,59 @@ class BaseCPU(SimObject): self.l2cache = l2c self.l2cache.cpu_side = self.toL2Bus.port self._mem_ports = ['l2cache.mem_side'] + + if build_env['TARGET_ISA'] == 'mips': + CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") + CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") + CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description") + CP0_EBase_CPUNum = Param.Unsigned(0,"No Description") + CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register") + CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register") + CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company") + CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register") + CP0_Config_BE = Param.Unsigned(0,"Big Endian?") + CP0_Config_AT = Param.Unsigned(0,"No Description") + CP0_Config_AR = Param.Unsigned(0,"No Description") + CP0_Config_MT = Param.Unsigned(0,"No Description") + CP0_Config_VI = Param.Unsigned(0,"No Description") + CP0_Config1_M = Param.Unsigned(0,"Config2 Implemented?") + CP0_Config1_MMU = Param.Unsigned(0,"MMU Type") + CP0_Config1_IS = Param.Unsigned(0,"No Description") + CP0_Config1_IL = Param.Unsigned(0,"No Description") + CP0_Config1_IA = Param.Unsigned(0,"No Description") + CP0_Config1_DS = Param.Unsigned(0,"No Description") + CP0_Config1_DL = Param.Unsigned(0,"No Description") + CP0_Config1_DA = Param.Unsigned(0,"No Description") + CP0_Config1_C2 = Param.Bool(False,"No Description") + CP0_Config1_MD = Param.Bool(False,"No Description") + CP0_Config1_PC = Param.Bool(False,"No Description") + CP0_Config1_WR = Param.Bool(False,"No Description") + CP0_Config1_CA = Param.Bool(False,"No Description") + CP0_Config1_EP = Param.Bool(False,"No Description") + CP0_Config1_FP = Param.Bool(False,"FPU Implemented?") + CP0_Config2_M = Param.Bool(False,"Config3 Implemented?") + CP0_Config2_TU = Param.Unsigned(0,"No Description") + CP0_Config2_TS = Param.Unsigned(0,"No Description") + CP0_Config2_TL = Param.Unsigned(0,"No Description") + CP0_Config2_TA = Param.Unsigned(0,"No Description") + CP0_Config2_SU = Param.Unsigned(0,"No Description") + CP0_Config2_SS = Param.Unsigned(0,"No Description") + CP0_Config2_SL = Param.Unsigned(0,"No Description") + CP0_Config2_SA = Param.Unsigned(0,"No Description") + CP0_Config3_M = Param.Bool(False,"Config4 Implemented?") + CP0_Config3_DSPP = Param.Bool(False,"DSP Extensions Present?") + CP0_Config3_LPA = Param.Bool(False,"No Description") + CP0_Config3_VEIC = Param.Bool(False,"No Description") + CP0_Config3_VInt = Param.Bool(False,"No Description") + CP0_Config3_SP = Param.Bool(False,"No Description") + CP0_Config3_MT = Param.Bool(False,"Multithreading Extensions Present?") + CP0_Config3_SM = Param.Bool(False,"No Description") + CP0_Config3_TL = Param.Bool(False,"No Description") + CP0_WatchHi_M = Param.Bool(False,"No Description") + CP0_PerfCtr_M = Param.Bool(False,"No Description") + CP0_PerfCtr_W = Param.Bool(False,"No Description") + CP0_PRId = Param.Unsigned(0,"CP0 Status Register") + CP0_Config = Param.Unsigned(0,"CP0 Config Register") + CP0_Config1 = Param.Unsigned(0,"CP0 Config1 Register") + CP0_Config2 = Param.Unsigned(0,"CP0 Config2 Register") + CP0_Config3 = Param.Unsigned(0,"CP0 Config3 Register") diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 3c3e91523..a0aa4d8f5 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -189,6 +189,77 @@ class BaseCPU : public MemObject Tick progress_interval; BaseCPU *checker; +#if THE_ISA == MIPS_ISA + /* Note: It looks like it will be better to allow simulator users + to specify the values of individual variables instead of requiring + users to define the values of entire registers + Especially since a lot of these variables can be created from other + user parameters (cache descriptions) + -jpp + */ + // MIPS CP0 State - First individual variables + // Page numbers refer to revision 2.50 (July 2005) of the MIPS32 ARM, Volume III (PRA) + unsigned CP0_IntCtl_IPTI; // Page 93, IP Timer Interrupt + unsigned CP0_IntCtl_IPPCI; // Page 94, IP Performance Counter Interrupt + unsigned CP0_SrsCtl_HSS; // Page 95, Highest Implemented Shadow Set + unsigned CP0_PRId_CompanyOptions; // Page 105, Manufacture options + unsigned CP0_PRId_CompanyID; // Page 105, Company ID - (0-255, 1=>MIPS) + unsigned CP0_PRId_ProcessorID; // Page 105 + unsigned CP0_PRId_Revision; // Page 105 + unsigned CP0_EBase_CPUNum; // Page 106, CPU Number in a multiprocessor system + unsigned CP0_Config_BE; // Page 108, Big/Little Endian mode + unsigned CP0_Config_AT; //Page 109 + unsigned CP0_Config_AR; //Page 109 + unsigned CP0_Config_MT; //Page 109 + unsigned CP0_Config_VI; //Page 109 + unsigned CP0_Config1_M; // Page 110 + unsigned CP0_Config1_MMU; // Page 110 + unsigned CP0_Config1_IS; // Page 110 + unsigned CP0_Config1_IL; // Page 111 + unsigned CP0_Config1_IA; // Page 111 + unsigned CP0_Config1_DS; // Page 111 + unsigned CP0_Config1_DL; // Page 112 + unsigned CP0_Config1_DA; // Page 112 + bool CP0_Config1_C2; // Page 112 + bool CP0_Config1_MD;// Page 112 - Technically not used in MIPS32 + bool CP0_Config1_PC;// Page 112 + bool CP0_Config1_WR;// Page 113 + bool CP0_Config1_CA;// Page 113 + bool CP0_Config1_EP;// Page 113 + bool CP0_Config1_FP;// Page 113 + bool CP0_Config2_M; // Page 114 + unsigned CP0_Config2_TU;// Page 114 + unsigned CP0_Config2_TS;// Page 114 + unsigned CP0_Config2_TL;// Page 115 + unsigned CP0_Config2_TA;// Page 115 + unsigned CP0_Config2_SU;// Page 115 + unsigned CP0_Config2_SS;// Page 115 + unsigned CP0_Config2_SL;// Page 116 + unsigned CP0_Config2_SA;// Page 116 + bool CP0_Config3_M; //// Page 117 + bool CP0_Config3_DSPP;// Page 117 + bool CP0_Config3_LPA;// Page 117 + bool CP0_Config3_VEIC;// Page 118 + bool CP0_Config3_VInt; // Page 118 + bool CP0_Config3_SP;// Page 118 + bool CP0_Config3_MT;// Page 119 + bool CP0_Config3_SM;// Page 119 + bool CP0_Config3_TL;// Page 119 + + bool CP0_WatchHi_M; // Page 124 + bool CP0_PerfCtr_M; // Page 130 + bool CP0_PerfCtr_W; // Page 130 + + + // Then, whole registers + unsigned CP0_PRId; + unsigned CP0_Config; + unsigned CP0_Config1; + unsigned CP0_Config2; + unsigned CP0_Config3; + +#endif + Params(); }; diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 55b385d11..24745735f 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -203,16 +203,6 @@ class O3ThreadContext : public ThreadContext /** Sets this thread's next PC. */ virtual void setNextPC(uint64_t val); - virtual uint64_t readMicroPC() - { return cpu->readMicroPC(thread->readTid()); } - - virtual void setMicroPC(uint64_t val); - - virtual uint64_t readNextMicroPC() - { return cpu->readNextMicroPC(thread->readTid()); } - - virtual void setNextMicroPC(uint64_t val); - /** Reads a miscellaneous register. */ virtual MiscReg readMiscRegNoEffect(int misc_reg) { return cpu->readMiscRegNoEffect(misc_reg, thread->readTid()); } @@ -246,6 +236,7 @@ class O3ThreadContext : public ThreadContext * misspeculating, this is set as false. */ virtual bool misspeculating() { return false; } + virtual void setShadowSet(int ss) { }; #if !FULL_SYSTEM /** Gets a syscall argument by index. */ virtual IntReg getSyscallArg(int i); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 98e29d8d1..e521837df 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -466,9 +466,9 @@ BaseSimpleCPU::advancePC(Fault fault) if (fault != NoFault) { curMacroStaticInst = StaticInst::nullStaticInstPtr; predecoder.reset(); + fault->invoke(tc); thread->setMicroPC(0); thread->setNextMicroPC(1); - fault->invoke(tc); } else { //If we're at the last micro op for this instruction if (curStaticInst && curStaticInst->isLastMicroop()) { @@ -503,3 +503,37 @@ BaseSimpleCPU::advancePC(Fault fault) } while (oldpc != thread->readPC()); } +Fault +BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr) +{ + // translate to physical address + Fault fault = NoFault; + int CacheID = Op & 0x3; // Lower 3 bits identify Cache + int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation + if(CacheID > 1) + { + warn("CacheOps not implemented for secondary/tertiary caches\n"); + } + else + { + switch(CacheOP) + { // Fill Packet Type + case 0: warn("Invalidate Cache Op\n"); + break; + case 1: warn("Index Load Tag Cache Op\n"); + break; + case 2: warn("Index Store Tag Cache Op\n"); + break; + case 4: warn("Hit Invalidate Cache Op\n"); + break; + case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n"); + break; + case 6: warn("Hit Writeback\n"); + break; + case 7: warn("Fetch & Lock Cache Op\n"); + break; + default: warn("Unimplemented Cache Op\n"); + } + } + return fault; +} diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index 337ef5285..5990e46b0 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -378,6 +378,12 @@ class BaseSimpleCPU : public BaseCPU "register access.\n"); } + void setShadowSet(int css) { + panic("Simple CPU models do not support Shadow Sets"); + //tc->setShadowSet(css); + } + + Fault CacheOp(uint8_t Op, Addr EA); #if FULL_SYSTEM Fault hwrei() { return thread->hwrei(); } void ev5_trap(Fault fault) { fault->invoke(tc); } diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 2b79c9708..cccb53322 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -368,6 +368,10 @@ class SimpleThread : public ThreadState void setStCondFailures(unsigned sc_failures) { storeCondFailures = sc_failures; } + void setShadowSet(int css, int tid=0) { + regs.setShadowSet(css); + } + #if !FULL_SYSTEM TheISA::IntReg getSyscallArg(int i) { diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh index c02c1c3bc..d2232bab7 100644 --- a/src/cpu/static_inst.hh +++ b/src/cpu/static_inst.hh @@ -114,6 +114,7 @@ class StaticInstBase : public RefCounted IsLoad, ///< Reads from memory (load or prefetch). IsStore, ///< Writes to memory. IsStoreConditional, ///< Store conditional instruction. + IsIndexed, ///< Accesses memory with an indexed address computation IsInstPrefetch, ///< Instruction-cache prefetch. IsDataPrefetch, ///< Data-cache prefetch. IsCopy, ///< Fast Cache block copy @@ -136,6 +137,7 @@ class StaticInstBase : public RefCounted IsSerializeAfter, IsMemBarrier, ///< Is a memory barrier IsWriteBarrier, ///< Is a write barrier + IsERET, /// <- Causes the IFU to stall (MIPS ISA) IsNonSpeculative, ///< Should not be executed speculatively IsQuiesce, ///< Is a quiesce instruction @@ -154,6 +156,7 @@ class StaticInstBase : public RefCounted IsFirstMicroop, ///< This microop begins a microop sequence //This flag doesn't do anything yet IsMicroBranch, ///< This microop branches within the microcode for a macroop + IsDspOp, NumFlags }; diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 0d09492ee..fd35efc91 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -226,14 +226,6 @@ class ThreadContext virtual void setNextNPC(uint64_t val) = 0; - virtual uint64_t readMicroPC() = 0; - - virtual void setMicroPC(uint64_t val) = 0; - - virtual uint64_t readNextMicroPC() = 0; - - virtual void setNextMicroPC(uint64_t val) = 0; - virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0; virtual MiscReg readMiscReg(int misc_reg) = 0; @@ -246,6 +238,8 @@ class ThreadContext virtual void setRegOtherThread(int misc_reg, const MiscReg &val, unsigned tid) { }; + virtual void setShadowSet(int css) = 0; + // Also not necessarily the best location for these two. Hopefully will go // away once we decide upon where st cond failures goes. virtual unsigned readStCondFailures() = 0; @@ -415,6 +409,10 @@ class ProxyThreadContext : public ThreadContext void setFloatRegBits(int reg_idx, FloatRegBits val) { actualTC->setFloatRegBits(reg_idx, val); } + void setShadowSet(int css){ + return actualTC->setShadowSet(css); + } + uint64_t readPC() { return actualTC->readPC(); } void setPC(uint64_t val) { actualTC->setPC(val); } @@ -427,14 +425,6 @@ class ProxyThreadContext : public ThreadContext void setNextNPC(uint64_t val) { actualTC->setNextNPC(val); } - uint64_t readMicroPC() { return actualTC->readMicroPC(); } - - void setMicroPC(uint64_t val) { actualTC->setMicroPC(val); } - - uint64_t readNextMicroPC() { return actualTC->readMicroPC(); } - - void setNextMicroPC(uint64_t val) { actualTC->setMicroPC(val); } - MiscReg readMiscRegNoEffect(int misc_reg) { return actualTC->readMiscRegNoEffect(misc_reg); } |