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-rw-r--r--src/cpu/inorder/cpu.hh1
-rw-r--r--src/cpu/simple_thread.cc3
-rw-r--r--src/cpu/simple_thread.hh3
-rw-r--r--src/cpu/thread_context.hh1
4 files changed, 0 insertions, 8 deletions
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 31010a01f..595a38ecc 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -77,7 +77,6 @@ class InOrderCPU : public BaseCPU
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
- typedef TheISA::RegFile RegFile;
typedef TheISA::MiscReg MiscReg;
//DynInstPtr TypeDefs
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index 2edaf8f55..dde63d7d9 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -110,7 +110,6 @@ SimpleThread::SimpleThread()
#endif
{
tc = new ProxyThreadContext<SimpleThread>(this);
- regs.clear();
}
SimpleThread::~SimpleThread()
@@ -191,7 +190,6 @@ void
SimpleThread::serialize(ostream &os)
{
ThreadState::serialize(os);
- regs.serialize(cpu, os);
SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
SERIALIZE_SCALAR(microPC);
@@ -207,7 +205,6 @@ void
SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
{
ThreadState::unserialize(cp, section);
- regs.unserialize(cpu, cp, section);
UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs);
UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
UNSERIALIZE_SCALAR(microPC);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 31e69bafe..90502fe9f 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -90,7 +90,6 @@ class TranslatingPort;
class SimpleThread : public ThreadState
{
protected:
- typedef TheISA::RegFile RegFile;
typedef TheISA::MachInst MachInst;
typedef TheISA::MiscReg MiscReg;
typedef TheISA::FloatReg FloatReg;
@@ -99,7 +98,6 @@ class SimpleThread : public ThreadState
typedef ThreadContext::Status Status;
protected:
- RegFile regs; // correct-path register context
union {
FloatReg f[TheISA::NumFloatRegs];
FloatRegBits i[TheISA::NumFloatRegs];
@@ -253,7 +251,6 @@ class SimpleThread : public ThreadState
void clearArchRegs()
{
- regs.clear();
microPC = 0;
nextMicroPC = 1;
PC = nextPC = nextNPC = 0;
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 49776858d..98d244994 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -79,7 +79,6 @@ namespace TheISA {
class ThreadContext
{
protected:
- typedef TheISA::RegFile RegFile;
typedef TheISA::MachInst MachInst;
typedef TheISA::IntReg IntReg;
typedef TheISA::FloatReg FloatReg;