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-rw-r--r--src/cpu/simple/timing.cc24
-rw-r--r--src/cpu/thread_state.cc5
2 files changed, 20 insertions, 9 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 45da7c3eb..fa7bb4f86 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -574,10 +574,16 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
return true;
}
- else {
- //Snooping a Coherence Request, do nothing
- return true;
+ else if (pkt->result == Packet::Nacked) {
+ assert(cpu->_status == IcacheWaitResponse);
+ pkt->reinitNacked();
+ if (!sendTiming(pkt)) {
+ cpu->_status = IcacheRetry;
+ cpu->ifetch_pkt = pkt;
+ }
}
+ //Snooping a Coherence Request, do nothing
+ return true;
}
void
@@ -663,10 +669,16 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
return true;
}
- else {
- //Snooping a coherence req, do nothing
- return true;
+ else if (pkt->result == Packet::Nacked) {
+ assert(cpu->_status == DcacheWaitResponse);
+ pkt->reinitNacked();
+ if (!sendTiming(pkt)) {
+ cpu->_status = DcacheRetry;
+ cpu->dcache_pkt = pkt;
+ }
}
+ //Snooping a Coherence Request, do nothing
+ return true;
}
void
diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index 4b65ca4b8..be8f822f2 100644
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -169,9 +169,8 @@ ThreadState::getMemPort()
return port;
/* Use this port to for syscall emulation writes to memory. */
- port = new TranslatingPort(csprintf("%s-%d-funcport",
- baseCpu->name(), tid),
- process->pTable, false);
+ port = new TranslatingPort(csprintf("%s-%d-funcport", baseCpu->name(), tid),
+ process, TranslatingPort::NextPage);
connectToMemFunc(port);