summaryrefslogtreecommitdiff
path: root/src/cpu
diff options
context:
space:
mode:
Diffstat (limited to 'src/cpu')
-rwxr-xr-xsrc/cpu/o3/SConscript2
-rw-r--r--src/cpu/ozone/SConscript2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript
index a1af620be..ad61ad228 100755
--- a/src/cpu/o3/SConscript
+++ b/src/cpu/o3/SConscript
@@ -75,7 +75,7 @@ if 'O3CPU' in env['CPU_MODELS']:
sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
if env['USE_CHECKER']:
- SimObject('m5/objects/O3Checker.py')
+ SimObject('O3Checker.py')
Source('checker_builder.cc')
if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
diff --git a/src/cpu/ozone/SConscript b/src/cpu/ozone/SConscript
index 601e80a72..cb2006456 100644
--- a/src/cpu/ozone/SConscript
+++ b/src/cpu/ozone/SConscript
@@ -45,5 +45,5 @@ if 'OzoneCPU' in env['CPU_MODELS']:
Source('lw_lsq.cc')
Source('rename_table.cc')
if env['USE_CHECKER']:
- SimObject('m5/objects/OzoneChecker.py')
+ SimObject('OzoneChecker.py')
Source('checker_builder.cc')