diff options
Diffstat (limited to 'src/cpu')
28 files changed, 82 insertions, 29 deletions
diff --git a/src/cpu/base.cc b/src/cpu/base.cc index 977769126..d8585567d 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -120,6 +120,8 @@ CPUProgressEvent::description() const BaseCPU::BaseCPU(Params *p) : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id), + _instMasterId(p->system->getMasterId(name() + ".inst")), + _dataMasterId(p->system->getMasterId(name() + ".data")), interrupts(p->interrupts), numThreads(p->numThreads), system(p->system), phase(p->phase) diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 8250338cc..93e5476ef 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -104,6 +104,12 @@ class BaseCPU : public MemObject // therefore no setCpuId() method is provided int _cpuId; + /** instruction side request id that must be placed in all requests */ + MasterID _instMasterId; + + /** data side request id that must be placed in all requests */ + MasterID _dataMasterId; + /** * Define a base class for the CPU ports (instruction and data) * that is refined in the subclasses. This class handles the @@ -144,6 +150,11 @@ class BaseCPU : public MemObject /** Reads this CPU's ID. */ int cpuId() { return _cpuId; } + /** Reads this CPU's unique data requestor ID */ + MasterID dataMasterId() { return _dataMasterId; } + /** Reads this CPU's unique instruction requestor ID */ + MasterID instMasterId() { return _instMasterId; } + // Tick currentTick; inline Tick frequency() const { return SimClock::Frequency / clock; } inline Tick ticks(int numCycles) const { return clock * numCycles; } diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 027e3f573..882d5ba41 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -424,6 +424,9 @@ class BaseDynInst : public FastAlloc, public RefCounted /** Read this CPU's ID. */ int cpuId() { return cpu->cpuId(); } + /** Read this CPU's data requestor ID */ + MasterID masterId() { return cpu->dataMasterId(); } + /** Read this context's system-wide ID **/ int contextId() { return thread->contextId(); } @@ -878,7 +881,7 @@ BaseDynInst<Impl>::readMem(Addr addr, uint8_t *data, sreqLow = savedSreqLow; sreqHigh = savedSreqHigh; } else { - req = new Request(asid, addr, size, flags, this->pc.instAddr(), + req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), thread->contextId(), threadNumber); // Only split the request if the ISA supports unaligned accesses. @@ -940,7 +943,7 @@ BaseDynInst<Impl>::writeMem(uint8_t *data, unsigned size, sreqLow = savedSreqLow; sreqHigh = savedSreqHigh; } else { - req = new Request(asid, addr, size, flags, this->pc.instAddr(), + req = new Request(asid, addr, size, flags, masterId(), this->pc.instAddr(), thread->contextId(), threadNumber); // Only split the request if the ISA supports unaligned accesses. diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc index 372d00c6f..fb381d24d 100644 --- a/src/cpu/checker/cpu.cc +++ b/src/cpu/checker/cpu.cc @@ -60,6 +60,7 @@ using namespace TheISA; void CheckerCPU::init() { + masterId = systemPtr->getMasterId(name()); } CheckerCPU::CheckerCPU(Params *p) @@ -241,7 +242,7 @@ CheckerCPU::writeMem(uint8_t *data, unsigned size, // Need to account for a multiple access like Atomic and Timing CPUs while (1) { memReq = new Request(); - memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr()); + memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr()); // translate to physical address fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write); diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 6f5125625..54e446932 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -93,6 +93,9 @@ class CheckerCPU : public BaseCPU typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; typedef TheISA::MiscReg MiscReg; + + /** id attached to all issued requests */ + MasterID masterId; public: virtual void init(); diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 7a99feb06..5688ee674 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -247,7 +247,7 @@ Checker<Impl>::verify(DynInstPtr &completed_inst) fetch_PC, thread->contextId(), unverifiedInst->threadNumber); memReq->setVirt(0, fetch_PC, sizeof(MachInst), - Request::INST_FETCH, thread->instAddr()); + Request::INST_FETCH, masterId, thread->instAddr()); fault = itb->translateFunctional(memReq, tc, BaseTLB::Execute); diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc index 0ab9f0579..33bd9e619 100644 --- a/src/cpu/inorder/resources/cache_unit.cc +++ b/src/cpu/inorder/resources/cache_unit.cc @@ -367,6 +367,7 @@ CacheUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req, if (cache_req->memReq == NULL) { cache_req->memReq = new Request(cpu->asid[tid], aligned_addr, acc_size, flags, + cpu->dataMasterId(), inst->instAddr(), cpu->readCpuId(), //@todo: use context id tid); @@ -379,6 +380,7 @@ CacheUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req, inst->split2ndAddr, acc_size, flags, + cpu->dataMasterId(), inst->instAddr(), cpu->readCpuId(), tid); @@ -1070,6 +1072,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt) inst->getMemAddr(), inst->totalSize, 0, + cpu->dataMasterId(), 0); split_pkt = new Packet(cache_req->memReq, cache_req->pktCmd, diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc index b32134e00..cc4b8b53e 100644 --- a/src/cpu/inorder/resources/fetch_unit.cc +++ b/src/cpu/inorder/resources/fetch_unit.cc @@ -159,7 +159,8 @@ FetchUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req, if (cache_req->memReq == NULL) { cache_req->memReq = new Request(tid, aligned_addr, acc_size, flags, - inst->instAddr(), cpu->readCpuId(), tid); + cpu->instMasterId(), inst->instAddr(), cpu->readCpuId(), + tid); DPRINTF(InOrderCachePort, "[sn:%i] Created memReq @%x, ->%x\n", inst->seqNum, &cache_req->memReq, cache_req->memReq); } diff --git a/src/cpu/inorder/resources/tlb_unit.hh b/src/cpu/inorder/resources/tlb_unit.hh index caccb5a9f..6846bdc87 100644 --- a/src/cpu/inorder/resources/tlb_unit.hh +++ b/src/cpu/inorder/resources/tlb_unit.hh @@ -118,7 +118,9 @@ class TLBUnitRequest : public ResourceRequest { req_size = sizeof(TheISA::MachInst); flags = 0; inst->fetchMemReq = new Request(inst->readTid(), aligned_addr, - req_size, flags, inst->instAddr(), + req_size, flags, + res->cpu->instMasterId(), + inst->instAddr(), res->cpu->readCpuId(), inst->readTid()); memReq = inst->fetchMemReq; @@ -132,7 +134,9 @@ class TLBUnitRequest : public ResourceRequest { } inst->dataMemReq = new Request(inst->readTid(), aligned_addr, - req_size, flags, inst->instAddr(), + req_size, flags, + res->cpu->dataMasterId(), + inst->instAddr(), res->cpu->readCpuId(), inst->readTid()); memReq = inst->dataMemReq; diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 0b4067f7e..3dca6e8ba 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -565,7 +565,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc) // Build request here. RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH, - pc, cpu->thread[tid]->contextId(), tid); + cpu->instMasterId(), pc, cpu->thread[tid]->contextId(), tid); memReq[tid] = mem_req; diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 24e2f1eb8..4b243e862 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -269,7 +269,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, dcache_latency = 0; while (1) { - req->setVirt(0, addr, size, flags, thread->pcState().instAddr()); + req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); // translate to physical address Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read); @@ -357,7 +357,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, dcache_latency = 0; while(1) { - req->setVirt(0, addr, size, flags, thread->pcState().instAddr()); + req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); // translate to physical address Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write); diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 02758ac04..9035ce973 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -346,7 +346,8 @@ BaseSimpleCPU::setupFetchRequest(Request *req) DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr); Addr fetchPC = (instAddr & PCMask) + fetchOffset; - req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instAddr); + req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instMasterId(), + instAddr); } diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 6cf7c582c..d71a96580 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -385,7 +385,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2, buildPacket(pkt1, req1, read); buildPacket(pkt2, req2, read); - req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags()); + req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), Packet::Broadcast); @@ -418,7 +418,7 @@ TimingSimpleCPU::readMem(Addr addr, uint8_t *data, } RequestPtr req = new Request(asid, addr, size, - flags, pc, _cpuId, tid); + flags, dataMasterId(), pc, _cpuId, tid); Addr split_addr = roundDown(addr + size - 1, block_size); assert(split_addr <= addr || split_addr - addr < block_size); @@ -488,7 +488,7 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, } RequestPtr req = new Request(asid, addr, size, - flags, pc, _cpuId, tid); + flags, dataMasterId(), pc, _cpuId, tid); Addr split_addr = roundDown(addr + size - 1, block_size); assert(split_addr <= addr || split_addr - addr < block_size); diff --git a/src/cpu/testers/directedtest/DirectedGenerator.cc b/src/cpu/testers/directedtest/DirectedGenerator.cc index 68ea55449..d69261cf0 100644 --- a/src/cpu/testers/directedtest/DirectedGenerator.cc +++ b/src/cpu/testers/directedtest/DirectedGenerator.cc @@ -28,9 +28,11 @@ */ #include "cpu/testers/directedtest/DirectedGenerator.hh" +#include "sim/system.hh" DirectedGenerator::DirectedGenerator(const Params *p) - : SimObject(p) + : SimObject(p), + masterId(p->system->getMasterId(name())) { m_num_cpus = p->num_cpus; m_directed_tester = NULL; diff --git a/src/cpu/testers/directedtest/DirectedGenerator.hh b/src/cpu/testers/directedtest/DirectedGenerator.hh index c156efff0..422a0ddb6 100644 --- a/src/cpu/testers/directedtest/DirectedGenerator.hh +++ b/src/cpu/testers/directedtest/DirectedGenerator.hh @@ -49,6 +49,7 @@ class DirectedGenerator : public SimObject protected: int m_num_cpus; + MasterID masterId; RubyDirectedTester* m_directed_tester; }; diff --git a/src/cpu/testers/directedtest/InvalidateGenerator.cc b/src/cpu/testers/directedtest/InvalidateGenerator.cc index 4d8271a05..f01e6fb50 100644 --- a/src/cpu/testers/directedtest/InvalidateGenerator.cc +++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc @@ -58,7 +58,7 @@ InvalidateGenerator::initiate() Packet::Command cmd; // For simplicity, requests are assumed to be 1 byte-sized - Request *req = new Request(m_address, 1, flags); + Request *req = new Request(m_address, 1, flags, masterId); // // Based on the current state, issue a load or a store diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py index af1970594..ccadc5b36 100644 --- a/src/cpu/testers/directedtest/RubyDirectedTester.py +++ b/src/cpu/testers/directedtest/RubyDirectedTester.py @@ -35,6 +35,7 @@ class DirectedGenerator(SimObject): type = 'DirectedGenerator' abstract = True num_cpus = Param.Int("num of cpus") + system = Param.System(Parent.any, "System we belong to") class SeriesRequestGenerator(DirectedGenerator): type = 'SeriesRequestGenerator' diff --git a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc index 4cf9aed1c..137d24b21 100644 --- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc +++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc @@ -59,7 +59,7 @@ SeriesRequestGenerator::initiate() Request::Flags flags; // For simplicity, requests are assumed to be 1 byte-sized - Request *req = new Request(m_address, 1, flags); + Request *req = new Request(m_address, 1, flags, masterId); Packet::Command cmd; if (m_issue_writes) { diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py index d5f456d69..6a3568379 100644 --- a/src/cpu/testers/memtest/MemTest.py +++ b/src/cpu/testers/memtest/MemTest.py @@ -52,3 +52,5 @@ class MemTest(MemObject): functional = Port("Port to the functional memory used for verification") suppress_func_warnings = Param.Bool(False, "suppress warnings when functional accesses fail.\n") + sys = Param.System(Parent.any, "System Parameter") + diff --git a/src/cpu/testers/memtest/memtest.cc b/src/cpu/testers/memtest/memtest.cc index d70dc96e6..2d0131a92 100644 --- a/src/cpu/testers/memtest/memtest.cc +++ b/src/cpu/testers/memtest/memtest.cc @@ -46,6 +46,7 @@ #include "mem/request.hh" #include "sim/sim_events.hh" #include "sim/stats.hh" +#include "sim/system.hh" using namespace std; @@ -132,6 +133,7 @@ MemTest::MemTest(const Params *p) percentFunctional(p->percent_functional), percentUncacheable(p->percent_uncacheable), issueDmas(p->issue_dmas), + masterId(p->sys->getMasterId(name())), progressInterval(p->progress_interval), nextProgressMessage(p->progress_interval), percentSourceUnaligned(p->percent_source_unaligned), @@ -321,11 +323,11 @@ MemTest::tick() if (issueDmas) { paddr &= ~((1 << dma_access_size) - 1); - req->setPhys(paddr, 1 << dma_access_size, flags); + req->setPhys(paddr, 1 << dma_access_size, flags, masterId); req->setThreadContext(id,0); } else { paddr &= ~((1 << access_size) - 1); - req->setPhys(paddr, 1 << access_size, flags); + req->setPhys(paddr, 1 << access_size, flags, masterId); req->setThreadContext(id,0); } assert(req->getSize() == 1); diff --git a/src/cpu/testers/memtest/memtest.hh b/src/cpu/testers/memtest/memtest.hh index 1a59914fd..208b34caf 100644 --- a/src/cpu/testers/memtest/memtest.hh +++ b/src/cpu/testers/memtest/memtest.hh @@ -138,6 +138,9 @@ class MemTest : public MemObject bool issueDmas; + /** Request id for all generated traffic */ + MasterID masterId; + int id; std::set<unsigned> outstandingAddrs; diff --git a/src/cpu/testers/networktest/NetworkTest.py b/src/cpu/testers/networktest/NetworkTest.py index 0a18ca938..b2eda9aa2 100644 --- a/src/cpu/testers/networktest/NetworkTest.py +++ b/src/cpu/testers/networktest/NetworkTest.py @@ -28,6 +28,7 @@ from MemObject import MemObject from m5.params import * +from m5.proxy import * class NetworkTest(MemObject): type = 'NetworkTest' @@ -41,3 +42,4 @@ class NetworkTest(MemObject): inj_rate = Param.Float(0.1, "Packet injection rate") precision = Param.Int(3, "Number of digits of precision after decimal point") test = Port("Port to the memory system to test") + system = Param.System(Parent.any, "System we belong to") diff --git a/src/cpu/testers/networktest/networktest.cc b/src/cpu/testers/networktest/networktest.cc index 56fcc46c4..3fe153c4e 100644 --- a/src/cpu/testers/networktest/networktest.cc +++ b/src/cpu/testers/networktest/networktest.cc @@ -44,6 +44,7 @@ #include "mem/request.hh" #include "sim/sim_events.hh" #include "sim/stats.hh" +#include "sim/system.hh" using namespace std; @@ -113,7 +114,8 @@ NetworkTest::NetworkTest(const Params *p) maxPackets(p->max_packets), trafficType(p->traffic_type), injRate(p->inj_rate), - precision(p->precision) + precision(p->precision), + masterId(p->system->getMasterId(name())) { // set up counters noResponseCycles = 0; @@ -263,17 +265,17 @@ NetworkTest::generatePkt() if (randomReqType == 0) { // generate packet for virtual network 0 requestType = MemCmd::ReadReq; - req->setPhys(paddr, access_size, flags); + req->setPhys(paddr, access_size, flags, masterId); } else if (randomReqType == 1) { // generate packet for virtual network 1 requestType = MemCmd::ReadReq; flags.set(Request::INST_FETCH); - req->setVirt(0, 0x0, access_size, flags, 0x0); + req->setVirt(0, 0x0, access_size, flags, 0x0, masterId); req->setPaddr(paddr); } else { // if (randomReqType == 2) // generate packet for virtual network 2 requestType = MemCmd::WriteReq; - req->setPhys(paddr, access_size, flags); + req->setPhys(paddr, access_size, flags, masterId); } req->setThreadContext(id,0); diff --git a/src/cpu/testers/networktest/networktest.hh b/src/cpu/testers/networktest/networktest.hh index c277cfbab..de67d41a0 100644 --- a/src/cpu/testers/networktest/networktest.hh +++ b/src/cpu/testers/networktest/networktest.hh @@ -134,6 +134,8 @@ class NetworkTest : public MemObject double injRate; int precision; + MasterID masterId; + void completeRequest(PacketPtr pkt); void generatePkt(); diff --git a/src/cpu/testers/rubytest/Check.cc b/src/cpu/testers/rubytest/Check.cc index 164fb56e1..2444a14ab 100644 --- a/src/cpu/testers/rubytest/Check.cc +++ b/src/cpu/testers/rubytest/Check.cc @@ -103,8 +103,8 @@ Check::initiatePrefetch() } // Prefetches are assumed to be 0 sized - Request *req = new Request(m_address.getAddress(), 0, flags, curTick(), - m_pc.getAddress()); + Request *req = new Request(m_address.getAddress(), 0, flags, + m_tester_ptr->masterId(), curTick(), m_pc.getAddress()); req->setThreadContext(index, 0); PacketPtr pkt = new Packet(req, cmd, port->idx); @@ -141,8 +141,8 @@ Check::initiateFlush() Request::Flags flags; - Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, curTick(), - m_pc.getAddress()); + Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, + m_tester_ptr->masterId(), curTick(), m_pc.getAddress()); Packet::Command cmd; @@ -176,7 +176,8 @@ Check::initiateAction() Address writeAddr(m_address.getAddress() + m_store_count); // Stores are assumed to be 1 byte-sized - Request *req = new Request(writeAddr.getAddress(), 1, flags, curTick(), + Request *req = new Request(writeAddr.getAddress(), 1, flags, + m_tester_ptr->masterId(), curTick(), m_pc.getAddress()); req->setThreadContext(index, 0); @@ -243,7 +244,7 @@ Check::initiateCheck() // Checks are sized depending on the number of bytes written Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, - curTick(), m_pc.getAddress()); + m_tester_ptr->masterId(), curTick(), m_pc.getAddress()); req->setThreadContext(index, 0); PacketPtr pkt = new Packet(req, MemCmd::ReadReq, port->idx); diff --git a/src/cpu/testers/rubytest/RubyTester.cc b/src/cpu/testers/rubytest/RubyTester.cc index 5040d9fae..81bb93253 100644 --- a/src/cpu/testers/rubytest/RubyTester.cc +++ b/src/cpu/testers/rubytest/RubyTester.cc @@ -36,9 +36,11 @@ #include "mem/ruby/eventqueue/RubyEventQueue.hh" #include "mem/ruby/system/System.hh" #include "sim/sim_exit.hh" +#include "sim/system.hh" RubyTester::RubyTester(const Params *p) : MemObject(p), checkStartEvent(this), + _masterId(p->system->getMasterId(name())), m_checks_to_complete(p->checks_to_complete), m_deadlock_threshold(p->deadlock_threshold), m_wakeup_frequency(p->wakeup_frequency), diff --git a/src/cpu/testers/rubytest/RubyTester.hh b/src/cpu/testers/rubytest/RubyTester.hh index 1c0147c7e..fae40a417 100644 --- a/src/cpu/testers/rubytest/RubyTester.hh +++ b/src/cpu/testers/rubytest/RubyTester.hh @@ -101,6 +101,7 @@ class RubyTester : public MemObject void print(std::ostream& out) const; bool getCheckFlush() { return m_check_flush; } + MasterID masterId() { return _masterId; } protected: class CheckStartEvent : public Event { @@ -117,6 +118,8 @@ class RubyTester : public MemObject CheckStartEvent checkStartEvent; + MasterID _masterId; + private: void hitCallback(NodeID proc, SubBlock* data); diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py index fd6e9aefd..fc0a60e11 100644 --- a/src/cpu/testers/rubytest/RubyTester.py +++ b/src/cpu/testers/rubytest/RubyTester.py @@ -37,3 +37,4 @@ class RubyTester(MemObject): deadlock_threshold = Param.Int(50000, "how often to check for deadlock") wakeup_frequency = Param.Int(10, "number of cycles between wakeups") check_flush = Param.Bool(False, "check cache flushing") + system = Param.System(Parent.any, "System we belong to") |